riscv/rocket-chip
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rocketchip: globals are for sissies

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This commit is contained in:
Wesley W. Terpstra
2016-09-15 00:38:46 -07:00
parent 644f8fe974
commit fb24e847fd
11 changed files with 74 additions and 66 deletions
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src/main/scala/coreplex/Coreplex.scala
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@ -32,7 +32,7 @@ trait HasCoreplexParameters {
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
lazy val globalAddrMap = p(rocketchip.GlobalAddrMap).get
lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
}
case class CoreplexConfig(