riscv/rocket-chip
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rocketchip: globals are for sissies

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This commit is contained in:
Wesley W. Terpstra
2016-09-15 00:38:46 -07:00
parent 644f8fe974
commit fb24e847fd
11 changed files with 74 additions and 66 deletions
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2
src/main/scala/coreplex/Configs.scala
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@ -146,7 +146,7 @@ class BaseCoreplexConfig extends Config (
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NCoreplexExtClients).get + site(NUncachedTileLinkPorts),
nCachelessClients = site(NCoreplexExtClients) + site(NUncachedTileLinkPorts),
maxClientXacts = max_int(
// L1 cache
site(DCacheKey).nMSHRs + 1 /* IOMSHR */,

2
src/main/scala/coreplex/Coreplex.scala
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@ -32,7 +32,7 @@ trait HasCoreplexParameters {
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
lazy val globalAddrMap = p(rocketchip.GlobalAddrMap).get
lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
}
case class CoreplexConfig(

10
src/main/scala/coreplex/TestConfigs.scala
View File

@ -24,7 +24,7 @@ class WithComparator extends Config(
(p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters(
targets = Seq("mem", "io:ext:testram").map(name =>
site(GlobalAddrMap).get(name).start.longValue),
site(GlobalAddrMap)(name).start.longValue),
width = 8,
operations = 1000,
atomics = site(UseAtomics),
@ -54,7 +54,7 @@ class WithMemtest extends Config(
}
case GeneratorKey => GeneratorParameters(
maxRequests = 128,
startAddress = site(GlobalAddrMap).get("mem").start)
startAddress = site(GlobalAddrMap)("mem").start)
case BuildGroundTest =>
(p: Parameters) => Module(new GeneratorTest()(p))
case _ => throw new CDEMatchError
@ -114,7 +114,7 @@ class WithNastiConverterTest extends Config(
}
case GeneratorKey => GeneratorParameters(
maxRequests = 128,
startAddress = site(GlobalAddrMap).get("mem").start)
startAddress = site(GlobalAddrMap)("mem").start)
case BuildGroundTest =>
(p: Parameters) => Module(new NastiConverterTest()(p))
case _ => throw new CDEMatchError
@ -134,7 +134,7 @@ class WithTraceGen extends Config(
val nSets = 32 // L2 NSets
val nWays = 1
val blockOffset = site(CacheBlockOffsetBits)
val baseAddr = site(GlobalAddrMap).get("mem").start
val baseAddr = site(GlobalAddrMap)("mem").start
val nBeats = site(MIFDataBeats)
List.tabulate(4 * nWays) { i =>
Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
@ -157,7 +157,7 @@ class WithPCIeMockupTest extends Config(
GroundTestTileSettings(1))
case GeneratorKey => GeneratorParameters(
maxRequests = 128,
startAddress = site(GlobalAddrMap).get("mem").start)
startAddress = site(GlobalAddrMap)("mem").start)
case BuildGroundTest =>
(p: Parameters) => p(TileId) match {
case 0 => Module(new GeneratorTest()(p))