riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

remove parameter ExtIOAddrMapEntries (#250)

Browse Source 
with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
This commit is contained in:
Yunsup Lee 2016-09-07 00:05:00 -07:00 committed by Andrew Waterman
parent b76612f357
commit fb05f5a07f
2 changed files with 2 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/rocketchip/Configs.scala
View File

@ -35,7 +35,7 @@ class BasePlatformConfig extends Config (
new AddrMap(entries)
}
lazy val externalAddrMap = new AddrMap(
site(ExtIOAddrMapEntries),
site(ExtraDevices).addrMapEntries ++ site(ExtMMIOPorts),
start = BigInt("50000000", 16),
collapse = true)
lazy val globalAddrMap = {
@ -131,12 +131,10 @@ class BasePlatformConfig extends Config (
case ExtraDevices => new EmptyDeviceBlock
case ExtraTopPorts => (p: Parameters) => new Bundle
case ExtMMIOPorts => Nil
case ExtIOAddrMapEntries =>
site(ExtraDevices).addrMapEntries ++ site(ExtMMIOPorts)
case NExtMMIOAXIChannels => 0
case NExtMMIOAHBChannels => 0
case NExtMMIOTLChannels => 0
case ExportMMIOPort => site(ExtIOAddrMapEntries).size > 0
case ExportMMIOPort => !externalAddrMap.isEmpty
case AsyncBusChannels => false
case NExtBusAXIChannels => 0
case NExternalClients => (if (site(NExtBusAXIChannels) > 0) 1 else 0) +

1
src/main/scala/rocketchip/RocketChip.scala
View File

@ -41,7 +41,6 @@ case object AsyncMemChannels extends Field[Boolean]
case object AsyncMMIOChannels extends Field[Boolean]
/** External address map settings */
case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]]
case object ExtIOAddrMapEntries extends Field[Seq[AddrMapEntry]]
/** Function for building Coreplex */
case object BuildCoreplex extends Field[Parameters => Coreplex]
/** Function for connecting coreplex extra ports to top-level extra ports */