From fa7ead6357675b50856a2d95fc3c14c61b731fa2 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Mon, 27 Mar 2017 15:19:05 -0700
Subject: [PATCH] Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO"

This reverts commit fb6498f2c30fc9fa13756e025e44dbca53108af7.
---
 src/main/scala/rocket/DCache.scala | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
index 1c17ff42..5f44cb00 100644
--- a/src/main/scala/rocket/DCache.scala
+++ b/src/main/scala/rocket/DCache.scala
@@ -87,8 +87,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack
 
   // I/O MSHRs
-  val uncachedInFlight = Reg(init = Vec.fill(cacheParams.nMMIOs)(false.B))
-  val uncachedReqs = Reg(Vec(cacheParams.nMMIOs, new HellaCacheReq))
+  val uncachedInFlight = Seq.fill(cacheParams.nMMIOs) { RegInit(Bool(false)) }
+  val uncachedReqs = Seq.fill(cacheParams.nMMIOs) { Reg(new HellaCacheReq) }
 
   // hit initiation path
   dataArb.io.in(3).valid := io.cpu.req.valid && isRead(io.cpu.req.bits.cmd)
@@ -285,10 +285,15 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   tl_out.a.bits := Mux(!s2_uncached, acquire, Mux(!s2_write, get, Mux(!pstore1_amo, put, atomics)))
 
   // Set pending bits for outstanding TileLink transaction
+  val a_sel = UIntToOH(a_source, cacheParams.nMMIOs)
   when (tl_out.a.fire()) {
     when (s2_uncached) {
-      uncachedInFlight(a_source) := true
-      uncachedReqs(a_source) := s2_req
+      (a_sel.toBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) =>
+        when (s) {
+          f := Bool(true)
+          r := s2_req
+        }
+      }
     }.otherwise {
       cached_grant_wait := true
     }
@@ -307,10 +312,14 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
       assert(cached_grant_wait, "A GrantData was unexpected by the dcache.")
       when(d_last) { cached_grant_wait := false }
     } .elsewhen (grantIsUncached) {
-      assert(d_last, "DCache MMIO responses must be single-beat")
-      assert(uncachedInFlight(tl_out.d.bits.source), "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle!
-      uncachedInFlight(tl_out.d.bits.source) := false
-      val req = uncachedReqs(tl_out.d.bits.source)
+      val d_sel = UIntToOH(tl_out.d.bits.source, cacheParams.nMMIOs)
+      val req = Mux1H(d_sel, uncachedReqs)
+      (d_sel.toBools zip uncachedInFlight) foreach { case (s, f) =>
+        when (s && d_last) {
+          assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle!
+          f := false
+        }
+      }
       when (grantIsUncachedData) {
         s2_data := tl_out.d.bits.data
         s2_req.cmd := M_XRD