riscv/rocket-chip
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Error: don't be an exception wrt. caching

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Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.

Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.
This commit is contained in:
Wesley W. Terpstra 2018-02-14 22:51:37 -08:00
parent e2e678d53d
commit fa412246b3
2 changed files with 28 additions and 22 deletions
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26
src/main/scala/devices/tilelink/Error.scala
View File

@ -10,7 +10,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import scala.math.min
case class ErrorParams(address: Seq[AddressSet], maxAtomic: Int, maxTransfer: Int)
case class ErrorParams(address: Seq[AddressSet], maxAtomic: Int, maxTransfer: Int, acquire: Boolean = false)
{
require (1 <= maxAtomic && maxAtomic <= maxTransfer && maxTransfer <= 4096)
}
@ -26,10 +26,10 @@ abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
Seq(TLManagerParameters(
address = params.address,
resources = device.reg("mem"),
regionType = RegionType.UNCACHEABLE,
regionType = if (params.acquire) RegionType.TRACKED else RegionType.UNCACHEABLE,
executable = true,
supportsAcquireT = xfer,
supportsAcquireB = xfer,
supportsAcquireT = if (params.acquire) xfer else TransferSizes.none,
supportsAcquireB = if (params.acquire) xfer else TransferSizes.none,
supportsGet = xfer,
supportsPutPartial = xfer,
supportsPutFull = xfer,
@ -52,19 +52,15 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
val (in, edge) = node.in(0)
val a = Queue(in.a, 1)
val c = Queue(in.c, 1)
val da = Wire(in.d)
val dc = Wire(in.d)
val a_last = edge.last(a)
val c_last = edge.last(c)
val da_last = edge.last(da)
val dc_last = edge.last(dc)
a.ready := (da.ready && da_last) || !a_last
da.valid := a.valid && a_last
val a_opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant)
val a_opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
da.bits.opcode := a_opcodes(a.bits.opcode)
da.bits.param := UInt(0) // toT, but error grants must be handled transiently (ie: you don't keep permissions)
da.bits.size := a.bits.size
@ -73,6 +69,13 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
da.bits.data := UInt(0)
da.bits.error := Bool(true)
if (params.acquire) {
val c = Queue(in.c, 1)
val dc = Wire(in.d)
val c_last = edge.last(c)
val dc_last = edge.last(dc)
c.ready := (dc.ready && dc_last) || !c_last
dc.valid := c.valid && c_last
@ -86,8 +89,11 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
// Combine response channels
TLArbiter.lowest(edge, in.d, dc, da)
} else {
in.d <> da
}
// We never probe or issue B requests; we are UNCACHED
// We never probe or issue B requests
in.b.valid := Bool(false)
// Sink GrantAcks

2
src/main/scala/tilelink/Parameters.scala
View File

@ -40,7 +40,7 @@ case class TLManagerParameters(
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHEABLE) // acquire -> uncached, tracked, cached
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet