riscv/rocket-chip
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Merge branch 'master' into pipeline-mmio

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Megan Wachs 2017-05-03 08:37:12 -07:00 committed by GitHub
commit f8c92d2669
1 changed files with 2 additions and 2 deletions
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src/main/scala/rocket/Frontend.scala
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@ -69,9 +69,9 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val icache = outer.icache.module val icache = outer.icache.module
val tlb = Module(new TLB(log2Ceil(coreInstBytes*fetchWidth), nTLBEntries)) val tlb = Module(new TLB(log2Ceil(coreInstBytes*fetchWidth), nTLBEntries))
val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 3, flow = true)) } val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 4, flow = true)) }
val s0_valid = io.cpu.req.valid || fq.io.enq.ready val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-2)
val s1_pc = Reg(UInt(width=vaddrBitsExtended)) val s1_pc = Reg(UInt(width=vaddrBitsExtended))
val s1_speculative = Reg(Bool()) val s1_speculative = Reg(Bool())
val s2_valid = Reg(init=Bool(true)) val s2_valid = Reg(init=Bool(true))