rocketchip: remove clint; it moves into coreplex

src/main/scala/rocketchip/ExampleTop.scala

@@ -13,7 +13,6 @@ class ExampleTop(q: Parameters) extends BaseTop(q)
     with PeripheryBootROM
     with PeripheryDebug
     with PeripheryExtInterrupts
-    with PeripheryCoreplexLocalInterrupter
     with PeripheryMasterMem
     with PeripheryMasterAXI4MMIO
     with PeripherySlave {
@@ -24,7 +23,6 @@ class ExampleTopBundle[+L <: ExampleTop](p: Parameters, l: L) extends BaseTopBun
     with PeripheryBootROMBundle
     with PeripheryDebugBundle
     with PeripheryExtInterruptsBundle
-    with PeripheryCoreplexLocalInterrupterBundle
     with PeripheryMasterMemBundle
     with PeripheryMasterAXI4MMIOBundle
     with PeripherySlaveBundle
@@ -33,7 +31,6 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](p: Parameter
     with PeripheryBootROMModule
     with PeripheryDebugModule
     with PeripheryExtInterruptsModule
-    with PeripheryCoreplexLocalInterrupterModule
     with PeripheryMasterMemModule
     with PeripheryMasterAXI4MMIOModule
     with PeripherySlaveModule

src/main/scala/rocketchip/Periphery.scala

@@ -274,34 +274,6 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
 
 /////
 
-trait PeripheryCoreplexLocalInterrupter extends LazyModule with HasPeripheryParameters {
-  implicit val p: Parameters
-  val peripheryBus: TLXbar
-
-  // CoreplexLocalInterrupter must be at least 64b if XLen >= 64
-  val beatBytes = max((outerMMIOParams(XLen) min 64) / 8, peripheryBusConfig.beatBytes)
-  val clintConfig = CoreplexLocalInterrupterConfig(beatBytes)
-  val clint = LazyModule(new CoreplexLocalInterrupter(clintConfig)(outerMMIOParams))
-  // The periphery bus is 32-bit, so we may need to adapt its width to XLen
-  clint.node := TLFragmenter(beatBytes, cacheBlockBytes)(TLWidthWidget(peripheryBusConfig.beatBytes)(peripheryBus.node))
-}
-
-trait PeripheryCoreplexLocalInterrupterBundle {
-  implicit val p: Parameters
-}
-
-trait PeripheryCoreplexLocalInterrupterModule extends HasPeripheryParameters {
-  implicit val p: Parameters
-  val outer: PeripheryCoreplexLocalInterrupter
-  val io: PeripheryCoreplexLocalInterrupterBundle
-  val coreplexIO: BaseCoreplexBundle
-
-  outer.clint.module.io.rtcTick := Counter(p(RTCPeriod)).inc()
-  coreplexIO.clint <> outer.clint.module.io.tiles
-}
-
-/////
-
 trait PeripheryBootROM extends LazyModule with HasPeripheryParameters {
   implicit val p: Parameters
   val peripheryBus: TLXbar

src/main/scala/rocketchip/Utils.scala

@@ -107,7 +107,7 @@ object GenerateConfigString {
   def apply(p: Parameters, c: CoreplexConfig, peripheryManagers: Seq[TLManagerParameters]) = {
     val addrMap = p(GlobalAddrMap)
     val plicAddr = addrMap("io:cbus:plic").start
-    val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:TL2:clint").start)
+    val clint = CoreplexLocalInterrupterConfig()
     val xLen = p(XLen)
     val res = new StringBuilder
     res append  "plic {\n"

src/main/scala/uncore/devices/Prci.scala

@@ -20,7 +20,7 @@ class CoreplexLocalInterrupts extends Bundle {
   val msip = Bool()
 }
 
-case class CoreplexLocalInterrupterConfig(beatBytes: Int, address: BigInt = 0x02000000) {
+case class CoreplexLocalInterrupterConfig(address: BigInt = 0x02000000) {
   def msipOffset(hart: Int) = hart * msipBytes
   def msipAddress(hart: Int) = address + msipOffset(hart)
   def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
@@ -48,8 +48,6 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
 
   val timeWidth = 64
   val regWidth = 32
-  // demand atomic accesses for RV64
-  require(c.beatBytes >= (p(rocket.XLen) min timeWidth)/8)
 
   val time = Seq.fill(timeWidth/regWidth)(Reg(init=UInt(0, width = regWidth)))
   when (io.rtcTick) {
@@ -87,6 +85,6 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
 /** Power, Reset, Clock, Interrupt */
 // Magic TL2 Incantation to create a TL2 Slave
 class CoreplexLocalInterrupter(c: CoreplexLocalInterrupterConfig)(implicit val p: Parameters)
-  extends TLRegisterRouter(c.address, 0, c.size, 0, c.beatBytes, false)(
+  extends TLRegisterRouter(c.address, size = c.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
   new TLRegBundle((c, p), _)    with CoreplexLocalInterrupterBundle)(
   new TLRegModule((c, p), _, _) with CoreplexLocalInterrupterModule)