riscv/rocket-chip
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rocketchip: remove clint; it moves into coreplex

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This commit is contained in:
Wesley W. Terpstra
2016-10-26 17:48:15 -07:00
parent 5090ff945b
commit f8a0829134
4 changed files with 3 additions and 36 deletions
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2
src/main/scala/rocketchip/Utils.scala
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@ -107,7 +107,7 @@ object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, peripheryManagers: Seq[TLManagerParameters]) = {
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("io:cbus:plic").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:TL2:clint").start)
val clint = CoreplexLocalInterrupterConfig()
val xLen = p(XLen)
val res = new StringBuilder
res append "plic {\n"