From f83d1d0aaf01f490b7c9816e764abb1bc8d47e76 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Mon, 31 Oct 2016 11:40:33 -0700
Subject: [PATCH] coreplex: rename trait CoreplexRISCVPlatform

This makes it clear we are talking about the devices one expects in the
platform, not the ISA.
---
 src/main/scala/coreplex/BaseCoreplex.scala | 18 +++++++++---------
 src/main/scala/coreplex/Coreplex.scala     | 10 +++++-----
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index 25d6a83c..89b0cb99 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -93,7 +93,7 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
   implicit val p = outer.p
 }
 
-trait CoreplexRISCV {
+trait CoreplexRISCVPlatform {
     this: CoreplexNetwork =>
 
   // Build a set of Tiles
@@ -118,9 +118,9 @@ trait CoreplexRISCV {
   tileIntNodes.foreach { _ := plic.intnode }
 }
 
-trait CoreplexRISCVBundle {
+trait CoreplexRISCVPlatformBundle {
   this: CoreplexNetworkBundle {
-    val outer: CoreplexRISCV
+    val outer: CoreplexRISCVPlatform
   } =>
 
   val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
@@ -131,10 +131,10 @@ trait CoreplexRISCVBundle {
   val success = Bool(OUTPUT) // used for testing
 }
 
-trait CoreplexRISCVModule {
+trait CoreplexRISCVPlatformModule {
   this: CoreplexNetworkModule {
-    val outer: CoreplexNetwork with CoreplexRISCV
-    val io: CoreplexRISCVBundle
+    val outer: CoreplexNetwork with CoreplexRISCVPlatform
+    val io: CoreplexRISCVPlatformBundle
   } =>
 
   val tiles = outer.lazyTiles.map(_.module)
@@ -231,14 +231,14 @@ trait CoreplexRISCVModule {
 
 class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
     with CoreplexNetwork
-    with CoreplexRISCV {
+    with CoreplexRISCVPlatform {
   override lazy val module = new BaseCoreplexModule(this, () => new BaseCoreplexBundle(this))
 }
 
 class BaseCoreplexBundle[+L <: BaseCoreplex](_outer: L) extends BareCoreplexBundle(_outer)
     with CoreplexNetworkBundle
-    with CoreplexRISCVBundle
+    with CoreplexRISCVPlatformBundle
 
 class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle[L]](_outer: L, _io: () => B) extends BareCoreplexModule(_outer, _io)
     with CoreplexNetworkModule
-    with CoreplexRISCVModule
+    with CoreplexRISCVPlatformModule
diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala
index 4a9e279a..ad8952d2 100644
--- a/src/main/scala/coreplex/Coreplex.scala
+++ b/src/main/scala/coreplex/Coreplex.scala
@@ -11,12 +11,12 @@ import util._
 import rocket._
 
 trait DirectConnection {
-    this: CoreplexNetwork with CoreplexRISCV =>
+    this: CoreplexNetwork with CoreplexRISCVPlatform =>
   lazyTiles.map(_.slave).flatten.foreach { scratch => scratch := cbus.node }
 }
 
 trait DirectConnectionModule {
-    this: CoreplexNetworkModule with CoreplexRISCVModule =>
+    this: CoreplexNetworkModule with CoreplexRISCVPlatformModule =>
 
   val tlBuffering = TileLinkDepths(1,1,2,2,0)
   val ultBuffering = UncachedTileLinkDepths(1,2)
@@ -45,7 +45,7 @@ class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L
 /////
 
 trait AsyncConnection {
-    this: CoreplexNetwork with CoreplexRISCV =>
+    this: CoreplexNetwork with CoreplexRISCVPlatform =>
   val crossings = lazyTiles.map(_.slave).map(_.map { scratch =>
     val crossing = LazyModule(new TLAsyncCrossing)
     crossing.node := cbus.node
@@ -55,7 +55,7 @@ trait AsyncConnection {
 }
 
 trait AsyncConnectionBundle {
-    this: CoreplexNetworkBundle with CoreplexRISCVBundle =>
+    this: CoreplexNetworkBundle with CoreplexRISCVPlatformBundle =>
   val tcrs = Vec(nTiles, new Bundle {
     val clock = Clock(INPUT)
     val reset = Bool(INPUT)
@@ -63,7 +63,7 @@ trait AsyncConnectionBundle {
 }
 
 trait AsyncConnectionModule {
-  this: Module with CoreplexNetworkModule with CoreplexRISCVModule {
+  this: Module with CoreplexNetworkModule with CoreplexRISCVPlatformModule {
     val outer: AsyncConnection
     val io: AsyncConnectionBundle
   } =>