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Remove subword load muxing in ScratchpadSlavePort

This commit is contained in:
Andrew Waterman 2017-05-01 17:36:39 -07:00
parent 044b6ed3f9
commit f8151ce786
4 changed files with 5 additions and 8 deletions

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@ -517,6 +517,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val loadgen = new LoadGen(s2_req.typ, mtSigned(s2_req.typ), s2_req.addr, s2_data_word, s2_sc, wordBytes) val loadgen = new LoadGen(s2_req.typ, mtSigned(s2_req.typ), s2_req.addr, s2_data_word, s2_sc, wordBytes)
io.cpu.resp.bits.data := loadgen.data | s2_sc_fail io.cpu.resp.bits.data := loadgen.data | s2_sc_fail
io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_word_bypass := loadgen.wordData
io.cpu.resp.bits.data_raw := s2_data_word
io.cpu.resp.bits.store_data := pstore1_data io.cpu.resp.bits.store_data := pstore1_data
// AMOs // AMOs

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@ -103,6 +103,7 @@ class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
val replay = Bool() val replay = Bool()
val has_data = Bool() val has_data = Bool()
val data_word_bypass = Bits(width = coreDataBits) val data_word_bypass = Bits(width = coreDataBits)
val data_raw = Bits(width = coreDataBits)
val store_data = Bits(width = coreDataBits) val store_data = Bits(width = coreDataBits)
} }

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@ -972,6 +972,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
io.cpu.s2_nack := s2_valid && s2_nack io.cpu.s2_nack := s2_valid && s2_nack
io.cpu.resp := Mux(mshrs.io.resp.ready, uncache_resp, cache_resp) io.cpu.resp := Mux(mshrs.io.resp.ready, uncache_resp, cache_resp)
io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_word_bypass := loadgen.wordData
io.cpu.resp.bits.data_raw := s2_data_word
io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next

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@ -48,7 +48,7 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
when (io.dmem.req.fire()) { state := s_wait } when (io.dmem.req.fire()) { state := s_wait }
val acq = Reg(tl_in.a.bits) val acq = Reg(tl_in.a.bits)
when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data } when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data_raw }
when (tl_in.a.fire()) { acq := tl_in.a.bits } when (tl_in.a.fire()) { acq := tl_in.a.bits }
def formCacheReq(a: TLBundleA) = { def formCacheReq(a: TLBundleA) = {
@ -85,17 +85,11 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
io.dmem.s1_kill := false io.dmem.s1_kill := false
io.dmem.invalidate_lr := false io.dmem.invalidate_lr := false
// place AMO data in correct word lane
val minAMOBytes = 4
val grantData = Mux(io.dmem.resp.valid, io.dmem.resp.bits.data, acq.data)
val alignedGrantData =
Mux(edge.hasData(acq) && (acq.size <= log2Ceil(minAMOBytes)), Fill(coreDataBytes/minAMOBytes, grantData(8*minAMOBytes-1, 0)), grantData)
tl_in.d.valid := io.dmem.resp.valid || state === s_grant tl_in.d.valid := io.dmem.resp.valid || state === s_grant
tl_in.d.bits := Mux(acq.opcode === TLMessages.PutFullData, tl_in.d.bits := Mux(acq.opcode === TLMessages.PutFullData,
edge.AccessAck(acq, UInt(0)), edge.AccessAck(acq, UInt(0)),
edge.AccessAck(acq, UInt(0), UInt(0))) edge.AccessAck(acq, UInt(0), UInt(0)))
tl_in.d.bits.data := alignedGrantData tl_in.d.bits.data := Mux(io.dmem.resp.valid, io.dmem.resp.bits.data_raw, acq.data)
// Tie off unused channels // Tie off unused channels
tl_in.b.valid := Bool(false) tl_in.b.valid := Bool(false)