riscv/rocket-chip
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Remove subword load muxing in ScratchpadSlavePort

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This commit is contained in:
Andrew Waterman
2017-05-01 17:36:39 -07:00
parent 044b6ed3f9
commit f8151ce786
4 changed files with 5 additions and 8 deletions
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10
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -48,7 +48,7 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
when (io.dmem.req.fire()) { state := s_wait }
val acq = Reg(tl_in.a.bits)
when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data }
when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data_raw }
when (tl_in.a.fire()) { acq := tl_in.a.bits }
def formCacheReq(a: TLBundleA) = {
@ -85,17 +85,11 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
io.dmem.s1_kill := false
io.dmem.invalidate_lr := false
// place AMO data in correct word lane
val minAMOBytes = 4
val grantData = Mux(io.dmem.resp.valid, io.dmem.resp.bits.data, acq.data)
val alignedGrantData =
Mux(edge.hasData(acq) && (acq.size <= log2Ceil(minAMOBytes)), Fill(coreDataBytes/minAMOBytes, grantData(8*minAMOBytes-1, 0)), grantData)
tl_in.d.valid := io.dmem.resp.valid || state === s_grant
tl_in.d.bits := Mux(acq.opcode === TLMessages.PutFullData,
edge.AccessAck(acq, UInt(0)),
edge.AccessAck(acq, UInt(0), UInt(0)))
tl_in.d.bits.data := alignedGrantData
tl_in.d.bits.data := Mux(io.dmem.resp.valid, io.dmem.resp.bits.data_raw, acq.data)
// Tie off unused channels
tl_in.b.valid := Bool(false)