riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

reduce HTIF clock divider for now

Browse Source
This commit is contained in:
Andrew Waterman 2012-05-03 04:21:11 -07:00
parent 00155f4bc4
commit f804c57bb0
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
uncore/slowio.scala
View File

@ -3,7 +3,7 @@ package rocket
import Chisel._ import Chisel._
import Constants._ import Constants._
class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Component class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val out_fast = new ioDecoupled()(data).flip val out_fast = new ioDecoupled()(data).flip
@ -15,8 +15,9 @@ class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Comp
val clk_slow = Bool(OUTPUT) val clk_slow = Bool(OUTPUT)
} }
val hold_cycles = if (hold_cycles_in == -1) divisor/4 else hold_cycles_in
require((divisor & (divisor-1)) == 0) require((divisor & (divisor-1)) == 0)
require(hold_cycles < divisor/2 && hold_cycles >= 2) require(hold_cycles < divisor/2 && hold_cycles >= 1)
val cnt = Reg() { UFix(width = log2up(divisor)) } val cnt = Reg() { UFix(width = log2up(divisor)) }
cnt := cnt + UFix(1) cnt := cnt + UFix(1)