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diplomacy: restore Monitor functionality

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This commit is contained in:
Wesley W. Terpstra
2017-01-29 17:25:14 -08:00
parent 972953868c
commit f7f52cc722
7 changed files with 65 additions and 79 deletions
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24
src/main/scala/uncore/tilelink2/Bundles.scala
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@ -210,11 +210,11 @@ final class DecoupledSnoop[+T <: Data](gen: T) extends Bundle
object DecoupledSnoop
{
def apply[T <: Data](i: DecoupledIO[T]) = {
val out = Wire(new DecoupledSnoop(i.bits))
out.ready := i.ready
out.valid := i.valid
out.bits := i.bits
def apply[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T]) = {
val out = Wire(new DecoupledSnoop(sink.bits))
out.ready := sink.ready
out.valid := source.valid
out.bits := source.bits
out
}
}
@ -230,13 +230,13 @@ class TLBundleSnoop(params: TLBundleParameters) extends TLBundleBase(params)
object TLBundleSnoop
{
def apply(x: TLBundle) = {
val out = Wire(new TLBundleSnoop(x.params))
out.a <> DecoupledSnoop(x.a)
out.b <> DecoupledSnoop(x.b)
out.c <> DecoupledSnoop(x.c)
out.d <> DecoupledSnoop(x.d)
out.e <> DecoupledSnoop(x.e)
def apply(source: TLBundle, sink: TLBundle) = {
val out = Wire(new TLBundleSnoop(sink.params))
out.a := DecoupledSnoop(source.a, sink.a)
out.b := DecoupledSnoop(sink.b, source.b)
out.c := DecoupledSnoop(source.c, sink.c)
out.d := DecoupledSnoop(sink.d, source.d)
out.e := DecoupledSnoop(source.e, sink.e)
out
}
}

7
src/main/scala/uncore/tilelink2/Monitor.scala
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@ -7,7 +7,7 @@ import chisel3.internal.sourceinfo.{SourceInfo, SourceLine}
import config._
import diplomacy._
case class TLMonitorArgs(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: SourceInfo, p: Parameters)
case class TLMonitorArgs(edge: () => Seq[TLEdge], sourceInfo: SourceInfo, p: Parameters)
abstract class TLMonitorBase(args: TLMonitorArgs) extends LazyModule()(args.p)
{
@ -16,11 +16,12 @@ abstract class TLMonitorBase(args: TLMonitorArgs) extends LazyModule()(args.p)
def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool): Unit
lazy val module = new LazyModuleImp(this) {
val edges = args.edge()
val io = new Bundle {
val in = args.gen().asInput
val in = Vec(edges.size, new TLBundleSnoop(TLBundleParameters.union(edges.map(_.bundle)))).flip
}
legalize(io.in, args.edge(), reset)
(edges zip io.in).foreach { case (e, in) => legalize(in, e, reset) }
}
}

85
src/main/scala/uncore/tilelink2/Nodes.scala
View File

@ -24,44 +24,47 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString
override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString
def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
val monitor = p(TLMonitorBuilder)(TLMonitorArgs(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo, p))
override def connect(bindings: () => Seq[(TLEdgeIn, TLBundle, TLBundle)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
val monitor = p(TLMonitorBuilder)(TLMonitorArgs(() => bindings().map(_._1), sourceInfo, p))
(monitor, () => {
bi <> bo
monitor.foreach { _.module.io.in := TLBundleSnoop(bo) }
if (p(TLCombinationalCheck)) {
// It is forbidden for valid to depend on ready in TL2
// If someone did that, then this will create a detectable combinational loop
bo.a.ready := bi.a.ready && bo.a.valid
bi.b.ready := bo.b.ready && bi.b.valid
bo.c.ready := bi.c.ready && bo.c.valid
bi.d.ready := bo.d.ready && bi.d.valid
bo.e.ready := bi.e.ready && bo.e.valid
}
if (p(TLCombinationalCheck)) {
// Randomly stall the transfers
val allow = LFSRNoiseMaker(5)
bi.a.valid := bo.a.valid && allow(0)
bo.a.ready := bi.a.ready && allow(0)
bo.b.valid := bi.b.valid && allow(1)
bi.b.ready := bo.b.ready && allow(1)
bi.c.valid := bo.c.valid && allow(2)
bo.c.ready := bi.c.ready && allow(2)
bo.d.valid := bi.d.valid && allow(3)
bi.d.ready := bo.d.ready && allow(3)
bi.e.valid := bo.e.valid && allow(4)
bo.e.ready := bi.e.ready && allow(4)
// Inject garbage whenever not valid
val bits_a = bo.a.bits.fromBits(LFSRNoiseMaker(bo.a.bits.asUInt.getWidth))
val bits_b = bi.b.bits.fromBits(LFSRNoiseMaker(bi.b.bits.asUInt.getWidth))
val bits_c = bo.c.bits.fromBits(LFSRNoiseMaker(bo.c.bits.asUInt.getWidth))
val bits_d = bi.d.bits.fromBits(LFSRNoiseMaker(bi.d.bits.asUInt.getWidth))
val bits_e = bo.e.bits.fromBits(LFSRNoiseMaker(bo.e.bits.asUInt.getWidth))
when (!bi.a.valid) { bi.a.bits := bits_a }
when (!bo.b.valid) { bo.b.bits := bits_b }
when (!bi.c.valid) { bi.c.bits := bits_c }
when (!bo.d.valid) { bo.d.bits := bits_d }
when (!bi.e.valid) { bi.e.bits := bits_e }
val eval = bindings ()
monitor.foreach { m => (eval zip m.module.io.in) foreach { case ((_,i,o), m) => m := TLBundleSnoop(o,i) } }
eval.foreach { case (_, bi, bo) =>
bi <> bo
if (p(TLCombinationalCheck)) {
// It is forbidden for valid to depend on ready in TL2
// If someone did that, then this will create a detectable combinational loop
bo.a.ready := bi.a.ready && bo.a.valid
bi.b.ready := bo.b.ready && bi.b.valid
bo.c.ready := bi.c.ready && bo.c.valid
bi.d.ready := bo.d.ready && bi.d.valid
bo.e.ready := bi.e.ready && bo.e.valid
}
if (p(TLCombinationalCheck)) {
// Randomly stall the transfers
val allow = LFSRNoiseMaker(5)
bi.a.valid := bo.a.valid && allow(0)
bo.a.ready := bi.a.ready && allow(0)
bo.b.valid := bi.b.valid && allow(1)
bi.b.ready := bo.b.ready && allow(1)
bi.c.valid := bo.c.valid && allow(2)
bo.c.ready := bi.c.ready && allow(2)
bo.d.valid := bi.d.valid && allow(3)
bi.d.ready := bo.d.ready && allow(3)
bi.e.valid := bo.e.valid && allow(4)
bo.e.ready := bi.e.ready && allow(4)
// Inject garbage whenever not valid
val bits_a = bo.a.bits.fromBits(LFSRNoiseMaker(bo.a.bits.asUInt.getWidth))
val bits_b = bi.b.bits.fromBits(LFSRNoiseMaker(bi.b.bits.asUInt.getWidth))
val bits_c = bo.c.bits.fromBits(LFSRNoiseMaker(bo.c.bits.asUInt.getWidth))
val bits_d = bi.d.bits.fromBits(LFSRNoiseMaker(bi.d.bits.asUInt.getWidth))
val bits_e = bo.e.bits.fromBits(LFSRNoiseMaker(bo.e.bits.asUInt.getWidth))
when (!bi.a.valid) { bi.a.bits := bits_a }
when (!bo.b.valid) { bo.b.bits := bits_b }
when (!bi.c.valid) { bi.c.bits := bits_c }
when (!bo.d.valid) { bo.d.bits := bits_d }
when (!bi.e.valid) { bi.e.bits := bits_e }
}
}
})
}
@ -159,10 +162,6 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor
override def labelI(ei: TLAsyncEdgeParameters) = ei.manager.depth.toString
override def labelO(eo: TLAsyncEdgeParameters) = eo.manager.depth.toString
def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
(None, () => { bi <> bo })
}
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
@ -193,10 +192,6 @@ object TLRationalImp extends NodeImp[TLClientPortParameters, TLManagerPortParame
def colour = "#00ff00" // green
def connect(bo: => TLRationalBundle, bi: => TLRationalBundle, ei: => TLEdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
(None, () => { bi <> bo })
}
override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLRationalBundle]): TLClientPortParameters =
pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLRationalBundle]): TLManagerPortParameters =