riscv/rocket-chip
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allow ExtraDevices to have client ports as well as MMIO ports

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This commit is contained in:
Howard Mao 2016-08-18 12:14:41 -07:00
parent d771f37e7e
commit f7c42499bb
3 changed files with 38 additions and 13 deletions
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27
src/main/scala/Configs.scala
View File

@ -94,9 +94,11 @@ class BasePlatformConfig extends Config (
}
res append "};\n"
for (device <- site(ExtraDevices)) {
val deviceName = device.addrMapEntry.name
val deviceRegion = addrMap("io:ext:" + deviceName)
res.append(device.makeConfigString(deviceRegion))
if (device.hasMMIOPort) {
val deviceName = device.addrMapEntry.name
val deviceRegion = addrMap("io:ext:" + deviceName)
res.append(device.makeConfigString(deviceRegion))
}
}
res append '\u0000'
res.toString.getBytes
@ -125,14 +127,18 @@ class BasePlatformConfig extends Config (
case ExtraTopPorts => (p: Parameters) => new Bundle
case ExtMMIOPorts => Nil
case ExtIOAddrMapEntries =>
site(ExtraDevices).map(_.addrMapEntry) ++ site(ExtMMIOPorts)
site(ExtraDevices)
.filter(_.hasMMIOPort)
.map(_.addrMapEntry) ++
site(ExtMMIOPorts)
case NExtMMIOAXIChannels => 0
case NExtMMIOAHBChannels => 0
case NExtMMIOTLChannels => 0
case ExportMMIOPort => (site(ExtraDevices).size + site(ExtMMIOPorts).size) > 0
case ExportMMIOPort => (site(ExtraDevices).filter(_.hasMMIOPort).size + site(ExtMMIOPorts).size) > 0
case AsyncBusChannels => false
case NExtBusAXIChannels => 0
case NExternalClients => if (site(NExtBusAXIChannels) > 1) 1 else 0
case NExternalClients => (if (site(NExtBusAXIChannels) > 1) 1 else 0) +
site(ExtraDevices).filter(_.hasClientPort).size
case ConnectExtraPorts =>
(out: Bundle, in: Bundle, p: Parameters) => out <> in
@ -257,11 +263,16 @@ class WithTestRAM extends Config(
case ExtraDevices => {
class TestRAMDevice extends Device {
val ramSize = 0x1000
def builder(port: ClientUncachedTileLinkIO, extra: Bundle, p: Parameters) {
def builder(
sPort: Option[ClientUncachedTileLinkIO],
mPort: Option[ClientUncachedTileLinkIO],
extra: Bundle, p: Parameters) {
val testram = Module(new TileLinkTestRAM(ramSize)(p))
testram.io <> port
testram.io <> sPort.get
}
def addrMapEntry = AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW)))
def hasClientPort = false
def hasMMIOPort = true
}
Seq(new TestRAMDevice)
}

7
src/main/scala/Devices.scala
View File

@ -9,7 +9,12 @@ case object ExtraTopPorts extends Field[Parameters => Bundle]
case object ExtraDevices extends Field[Seq[Device]]
abstract class Device {
def builder(port: ClientUncachedTileLinkIO, extra: Bundle, p: Parameters): Unit
def hasMMIOPort: Boolean
def hasClientPort: Boolean
def builder(
mmioPort: Option[ClientUncachedTileLinkIO],
clientPort: Option[ClientUncachedTileLinkIO],
extra: Bundle, p: Parameters): Unit
def addrMapEntry: AddrMapEntry
def makeConfigString(region: MemRegion): String = {
s"${addrMapEntry.name} {\n" +

17
src/main/scala/RocketChip.scala
View File

@ -190,14 +190,15 @@ class Periphery(implicit val p: Parameters) extends Module
val extra = p(ExtraTopPorts)(p)
}
require(io.clients_out.size <= 1)
var client_ind = 0
if (io.clients_out.size > 0) {
if (io.bus_axi.size > 0) {
val conv = Module(new TileLinkIONastiIOConverter)
val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
val arb = Module(new NastiArbiter(io.bus_axi.size))
arb.io.master <> io.bus_axi
conv.io.nasti <> conv.io.tl
io.clients_out.head <> conv.io.tl
client_ind += 1
}
def connectExternalMMIO(ports: Seq[ClientUncachedTileLinkIO])(implicit p: Parameters) {
@ -231,7 +232,15 @@ class Periphery(implicit val p: Parameters) extends Module
mmioNetwork.io.in.head <> io.mmio_in.get
for (device <- p(ExtraDevices)) {
device.builder(mmioNetwork.port(device.addrMapEntry.name), io.extra, p)
val mmioPort = if (device.hasMMIOPort)
Some(mmioNetwork.port(device.addrMapEntry.name)) else None
val clientPort = if (device.hasClientPort) {
client_ind += 1
Some(io.clients_out(client_ind - 1))
} else None
device.builder(mmioPort, clientPort, io.extra, p)
}
val ext = p(ExtMMIOPorts).map(