riscv/rocket-chip
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put memory into the address map and no longer use MMIOBase

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This commit is contained in:
Howard Mao 2016-04-21 15:47:46 -07:00 committed by Andrew Waterman
parent 325d3671c4
commit f7af908969
8 changed files with 30 additions and 26 deletions
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2
chisel2

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Subproject commit 1ee157fea9bc5816bce04aadaa554b8970cb8871
Subproject commit c736c900aed0dc71f5d1189044ef902f6a3627f6

2
firrtl

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Subproject commit 484262d6ce6979276853cbe202fc038b4700ce2d
Subproject commit ec32c852b57a42c7741f8ae27d59c21fcdb86a82

2
groundtest

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Subproject commit 88de2b8e0a8b5e6e0e672cccdf1ddc25c6698374
Subproject commit 0204a9679bf1c2e79e6e603fd555abaf9892d0f5

2
junctions

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Subproject commit f49e4bbb2910959f326218ff6f86a671c4e1c412
Subproject commit cd3d2ca2190f1c16fa65840dbc86527e50613b5f

2
rocket

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Subproject commit f519082ff320f34ae7971c5590c8c8a919857cf4
Subproject commit bcc378aa717daf1a3dfcadd6cd1f77c58ba3ed47

13
src/main/scala/Configs.scala
View File

@ -35,9 +35,10 @@ class DefaultConfig extends Config (
new AddrMap(deviceTree +: csrs :+ scr)
}
def makeConfigString() = {
val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase))
val addrMap = new AddrHashMap(site(GlobalAddrMap))
val xLen = site(XLen)
val res = new StringBuilder
val memSize = addrMap(s"mem").size
res append "platform {\n"
res append " vendor ucb;\n"
res append " arch rocket;\n"
@ -45,7 +46,7 @@ class DefaultConfig extends Config (
res append "ram {\n"
res append " 0 {\n"
res append " addr 0;\n"
res append s" size 0x${site(MMIOBase).toString(16)};\n"
res append s" size 0x${memSize.toString(16)};\n"
res append " };\n"
res append "};\n"
res append "core {\n"
@ -222,11 +223,11 @@ class DefaultConfig extends Config (
maxClientsPerPort = site(MaxBanksPerMemoryChannel),
dataBeats = site(MIFDataBeats))
case TLKey("L2toMMIO") => {
val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase))
val addrMap = new AddrHashMap(site(GlobalAddrMap))
TileLinkParameters(
coherencePolicy = new MICoherence(
new NullRepresentation(site(NBanksPerMemoryChannel))),
nManagers = addrMap.nEntries,
nManagers = addrMap.nEntries - 1,
nCachingClients = 0,
nCachelessClients = 1,
maxClientXacts = 4,
@ -246,10 +247,12 @@ class DefaultConfig extends Config (
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
case UseBackupMemoryPort => false
case UseHtifClockDiv => true
case MMIOBase => Dump("MEM_SIZE", BigInt(1L << 30)) // 1 GB
case ConfigString => makeConfigString()
case GlobalAddrMap => {
val memsize = BigInt(1L << 30)
Dump("MEM_SIZE", memsize)
AddrMap(
AddrMapEntry("mem", None, MemSize(memsize, AddrMapConsts.RWX, true)),
AddrMapEntry("conf", None,
MemSubmap(BigInt(1L << 30), genCsrAddrMap)),
AddrMapEntry("devices", None,

31
src/main/scala/RocketChip.scala
View File

@ -169,14 +169,14 @@ class Uncore(implicit val p: Parameters) extends Module
}
// Arbitrate SCR access between MMIO and HTIF
val addrHashMap = new AddrHashMap(p(GlobalAddrMap), p(MMIOBase))
val addrHashMap = new AddrHashMap(p(GlobalAddrMap))
val scrFile = Module(new SCRFile("UNCORE_SCR",addrHashMap("conf:scr").start))
val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
scrArb.io.in(0) <> htif.io.scr
scrArb.io.in(1) <> outmemsys.io.scr
scrFile.io.smi <> scrArb.io.out
scrFile.io.scr.attach(Wire(init = UInt(nTiles)), "N_CORES")
scrFile.io.scr.attach(Wire(init = UInt(p(MMIOBase) >> 20)), "MMIO_BASE")
scrFile.io.scr.attach(Wire(init = UInt(addrHashMap("mem").size >> 20)), "MMIO_BASE")
// scrFile.io.scr <> (... your SCR connections ...)
// Configures the enabled memory channels. This can't be changed while the
@ -221,16 +221,18 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val deviceTree = new NastiIO
}
val mmioBase = p(MMIOBase)
val rtc = Module(new RTC(CSRs.mtime))
val addrMap = p(GlobalAddrMap)
val addrHashMap = new AddrHashMap(addrMap)
val memSize = addrHashMap("mem").size
// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
// Cached ports are first in client list, making sharerToClientId just an indentity function
// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
def sharerToClientId(sharerId: UInt) = sharerId
def addrToBank(addr: Bits): UInt = {
Mux(addr.toUInt < UInt(mmioBase >> log2Up(p(CacheBlockBytes))),
val isMemory = addrHashMap.isInRegion("mem",
addr.toUInt << log2Up(p(CacheBlockBytes)))
Mux(isMemory,
if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
UInt(nBanks))
}
@ -247,6 +249,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
case OuterTLId => "L2toMMIO"
})))
val rtc = Module(new RTC(CSRs.mtime))
// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
// and coherence manager(s) to the other side
l1tol2net.io.clients_cached <> io.tiles_cached
@ -258,13 +262,10 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val outermostTLParams = p.alterPartial({case TLId => "Outermost"})
val backendBuffering = TileLinkDepths(0,0,0,0,0)
val addrMap = p(GlobalAddrMap)
val addrHashMap = new AddrHashMap(addrMap, mmioBase)
val nSlaves = addrHashMap.nEntries
// TODO: the code to print this stuff should live somewhere else
println("Generated Address Map")
for ((name, base, size, _) <- addrHashMap.sortedEntries) {
for ((name, base, size, _, _) <- addrHashMap.sortedEntries) {
println(f"\t$name%s $base%x - ${base + size - 1}%x")
}
println("Generated Configuration String")
@ -298,7 +299,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val mmio_narrow = Module(new TileLinkIONarrower("L2toMMIO", "MMIO_Outermost"))
val mmio_net = Module(new TileLinkRecursiveInterconnect(
1, addrHashMap.nEntries, addrMap, mmioBase)(mmioOutermostTLParams))
1, addrHashMap.nEntries - 1, addrMap.tail, memSize)(mmioOutermostTLParams))
//val mmio_conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
mmio_narrow.io.in <> mmioManager.io.outer
@ -312,13 +313,13 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
for (i <- 0 until nTiles) {
val csrName = s"conf:csr$i"
val csrPort = addrHashMap(csrName).port
val csrPort = addrHashMap(csrName).port - 1
val conv = Module(new SmiIONastiIOConverter(xLen, csrAddrBits))
connectTilelinkNasti(conv.io.nasti, mmio_net.io.out(csrPort))(mmioOutermostTLParams)
io.csr(i) <> conv.io.smi
}
val scrPort = addrHashMap("conf:scr").port
val scrPort = addrHashMap("conf:scr").port - 1
val scr_conv = Module(new SmiIONastiIOConverter(scrDataBits, scrAddrBits))
connectTilelinkNasti(scr_conv.io.nasti, mmio_net.io.out(scrPort))(mmioOutermostTLParams)
io.scr <> scr_conv.io.smi
@ -327,12 +328,12 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val lo_width = p(StreamLoopbackWidth)
val lo_size = p(StreamLoopbackSize)
val lo_conv = Module(new NastiIOStreamIOConverter(lo_width))
val lo_port = addrHashMap("devices:loopback").port
val lo_port = addrHashMap("devices:loopback").port - 1
connectTilelinkNasti(lo_conv.io.nasti, mmio_net.io.out(lo_port))(mmioOutermostTLParams)
lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size)
}
val dtPort = addrHashMap("conf:devicetree").port
val dtPort = addrHashMap("conf:devicetree").port - 1
connectTilelinkNasti(io.deviceTree, mmio_net.io.out(dtPort))(mmioOutermostTLParams)
val mem_channels = Wire(Vec(nMemChannels, new NastiIO))

2
uncore

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Subproject commit 83bcedf87be79fffb5372cc66c61312bf28eadcc
Subproject commit 6aac33ff3eefdca9e0eda2540e7f4a311cd3c02c