riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: fix TL MMIO port example

Browse Source
This commit is contained in:
Wesley W. Terpstra 2018-01-05 12:27:18 +01:00
parent 206892899f
commit f749e986cf
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/Ports.scala
View File

@ -195,7 +195,7 @@ trait HasMasterTLMMIOPortBundle {
trait HasMasterTLMMIOPortModuleImp extends LazyModuleImp with HasMasterTLMMIOPortBundle {
val outer: HasMasterTLMMIOPort
val mmio_tl = IO(HeterogeneousBag.fromNode(outer.mmio_tl.in))
(mmio_tl zip outer.mmio_tl.out) foreach { case (i, (o, _)) => i <> o }
(mmio_tl zip outer.mmio_tl.in) foreach { case (i, (o, _)) => i <> o }
}
/** Adds an TL port to the system intended to be a slave on an MMIO device bus.