From f6f40b1442c3ed3051a9dd2172f306cefae08327 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 17 May 2017 11:37:23 -0700
Subject: [PATCH] unit tests: all should accept timeout override

---
 src/main/scala/uncore/ahb/Test.scala                     | 4 ++--
 src/main/scala/uncore/apb/Test.scala                     | 2 +-
 src/main/scala/uncore/axi4/Test.scala                    | 6 +++---
 src/main/scala/uncore/devices/Rom.scala                  | 2 +-
 src/main/scala/uncore/tilelink2/Arbiter.scala            | 2 +-
 src/main/scala/uncore/tilelink2/AsyncCrossing.scala      | 2 +-
 src/main/scala/uncore/tilelink2/AtomicAutomata.scala     | 2 +-
 src/main/scala/uncore/tilelink2/Fragmenter.scala         | 2 +-
 src/main/scala/uncore/tilelink2/Fuzzer.scala             | 2 +-
 src/main/scala/uncore/tilelink2/HintHandler.scala        | 2 +-
 src/main/scala/uncore/tilelink2/Nodes.scala              | 2 +-
 src/main/scala/uncore/tilelink2/RationalCrossing.scala   | 2 +-
 src/main/scala/uncore/tilelink2/RegisterRouterTest.scala | 4 ++--
 src/main/scala/uncore/tilelink2/SRAM.scala               | 2 +-
 src/main/scala/uncore/tilelink2/TestRAM.scala            | 2 +-
 src/main/scala/uncore/tilelink2/WidthWidget.scala        | 2 +-
 src/main/scala/uncore/tilelink2/Xbar.scala               | 4 ++--
 17 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/src/main/scala/uncore/ahb/Test.scala b/src/main/scala/uncore/ahb/Test.scala
index 05aa5da9..abfd4128 100644
--- a/src/main/scala/uncore/ahb/Test.scala
+++ b/src/main/scala/uncore/ahb/Test.scala
@@ -34,7 +34,7 @@ class AHBFuzzNative(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBNativeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
+class AHBNativeTest(aFlow: Boolean, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AHBFuzzNative(aFlow)).module)
   io.finished := dut.io.finished
 }
@@ -95,7 +95,7 @@ class AHBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBBridgeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
+class AHBBridgeTest(aFlow: Boolean, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AHBFuzzBridge(aFlow)).module)
   io.finished := dut.io.finished
 }
diff --git a/src/main/scala/uncore/apb/Test.scala b/src/main/scala/uncore/apb/Test.scala
index 80d707a4..dccdba8a 100644
--- a/src/main/scala/uncore/apb/Test.scala
+++ b/src/main/scala/uncore/apb/Test.scala
@@ -39,7 +39,7 @@ class APBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class APBBridgeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
+class APBBridgeTest(aFlow: Boolean, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new APBFuzzBridge(aFlow)).module)
   io.finished := dut.io.finished
 }
diff --git a/src/main/scala/uncore/axi4/Test.scala b/src/main/scala/uncore/axi4/Test.scala
index 6eab607d..dcc68b0a 100644
--- a/src/main/scala/uncore/axi4/Test.scala
+++ b/src/main/scala/uncore/axi4/Test.scala
@@ -34,7 +34,7 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AXI4LiteFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) {
+class AXI4LiteFuzzRAMTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AXI4LiteFuzzRAM).module)
   io.finished := dut.io.finished
 }
@@ -57,7 +57,7 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AXI4FullFuzzRAMTest(implicit p: Parameters) extends UnitTest(500000) {
+class AXI4FullFuzzRAMTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AXI4FullFuzzRAM).module)
   io.finished := dut.io.finished
 }
@@ -132,7 +132,7 @@ class AXI4FuzzBridge()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AXI4BridgeTest()(implicit p: Parameters) extends UnitTest(500000) {
+class AXI4BridgeTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new AXI4FuzzBridge).module)
   io.finished := dut.io.finished
 }
diff --git a/src/main/scala/uncore/devices/Rom.scala b/src/main/scala/uncore/devices/Rom.scala
index 55ef3992..929e440e 100644
--- a/src/main/scala/uncore/devices/Rom.scala
+++ b/src/main/scala/uncore/devices/Rom.scala
@@ -88,7 +88,7 @@ class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
     data = rdata)
 }
 
-class ROMSlaveTest(implicit p: Parameters) extends UnitTest {
+class ROMSlaveTest(timeout: Int = 4096)(implicit p: Parameters) extends UnitTest(timeout) {
   val romdata = Seq(
     BigInt("01234567deadbeef", 16),
     BigInt("ab32fee8d00dfeed", 16))
diff --git a/src/main/scala/uncore/tilelink2/Arbiter.scala b/src/main/scala/uncore/tilelink2/Arbiter.scala
index 2a99f843..54e985ac 100644
--- a/src/main/scala/uncore/tilelink2/Arbiter.scala
+++ b/src/main/scala/uncore/tilelink2/Arbiter.scala
@@ -94,7 +94,7 @@ object TLArbiter
 /** Synthesizeable unit tests */
 import unittest._
 
-class TestRobin()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TestRobin(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val sources = Wire(Vec(6, DecoupledIO(UInt(width=3))))
   val sink = Wire(DecoupledIO(UInt(width=3)))
   val count = RegInit(UInt(0, width=8))
diff --git a/src/main/scala/uncore/tilelink2/AsyncCrossing.scala b/src/main/scala/uncore/tilelink2/AsyncCrossing.scala
index bd2788ea..58308822 100644
--- a/src/main/scala/uncore/tilelink2/AsyncCrossing.scala
+++ b/src/main/scala/uncore/tilelink2/AsyncCrossing.scala
@@ -168,6 +168,6 @@ class TLRAMAsyncCrossing(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMAsyncCrossingTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMAsyncCrossingTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLRAMAsyncCrossing).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala
index ba9a444d..79730abc 100644
--- a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala
+++ b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala
@@ -306,6 +306,6 @@ class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMAtomicAutomataTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMAtomicAutomataTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLRAMAtomicAutomata).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala
index f30e579a..bd8dd7e7 100644
--- a/src/main/scala/uncore/tilelink2/Fragmenter.scala
+++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala
@@ -309,6 +309,6 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) e
   }
 }
 
-class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/Fuzzer.scala b/src/main/scala/uncore/tilelink2/Fuzzer.scala
index a55d4d44..4eb2288b 100644
--- a/src/main/scala/uncore/tilelink2/Fuzzer.scala
+++ b/src/main/scala/uncore/tilelink2/Fuzzer.scala
@@ -251,7 +251,7 @@ class TLFuzzRAM()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class TLFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) {
+class TLFuzzRAMTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val dut = Module(LazyModule(new TLFuzzRAM).module)
   io.finished := dut.io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/HintHandler.scala b/src/main/scala/uncore/tilelink2/HintHandler.scala
index 5e153e0c..e52bfaaf 100644
--- a/src/main/scala/uncore/tilelink2/HintHandler.scala
+++ b/src/main/scala/uncore/tilelink2/HintHandler.scala
@@ -123,6 +123,6 @@ class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMHintHandlerTest()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMHintHandlerTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLRAMHintHandler).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala
index cc8a58d9..51c4626f 100644
--- a/src/main/scala/uncore/tilelink2/Nodes.scala
+++ b/src/main/scala/uncore/tilelink2/Nodes.scala
@@ -106,7 +106,7 @@ case class TLInternalInputNode(portParams: Seq[TLClientPortParameters]) extends
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLInputNodeTest()(implicit p: Parameters) extends UnitTest(500000) {
+class TLInputNodeTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   class Acceptor extends LazyModule {
     val node = TLInputNode()
     val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
diff --git a/src/main/scala/uncore/tilelink2/RationalCrossing.scala b/src/main/scala/uncore/tilelink2/RationalCrossing.scala
index 4cfa94c9..84727ae0 100644
--- a/src/main/scala/uncore/tilelink2/RationalCrossing.scala
+++ b/src/main/scala/uncore/tilelink2/RationalCrossing.scala
@@ -222,6 +222,6 @@ class TLRAMRationalCrossing(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMRationalCrossingTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMRationalCrossingTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLRAMRationalCrossing).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
index febf91cd..74072c24 100644
--- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
+++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
@@ -266,7 +266,7 @@ class FuzzRRTest0()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRR0Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRR0Test(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new FuzzRRTest0).module).io.finished
 }
 
@@ -281,7 +281,7 @@ class FuzzRRTest1()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRR1Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRR1Test(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new FuzzRRTest1).module).io.finished
 }
 
diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala
index 25d36d5a..b0fe86f5 100644
--- a/src/main/scala/uncore/tilelink2/SRAM.scala
+++ b/src/main/scala/uncore/tilelink2/SRAM.scala
@@ -104,6 +104,6 @@ class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class TLRAMSimpleTest(ramBeatBytes: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMSimpleTest(ramBeatBytes: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/TestRAM.scala b/src/main/scala/uncore/tilelink2/TestRAM.scala
index bab75674..f2951492 100644
--- a/src/main/scala/uncore/tilelink2/TestRAM.scala
+++ b/src/main/scala/uncore/tilelink2/TestRAM.scala
@@ -78,6 +78,6 @@ class TLRAMZeroDelay(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModu
   }
 }
 
-class TLRAMZeroDelayTest(ramBeatBytes: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMZeroDelayTest(ramBeatBytes: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/WidthWidget.scala b/src/main/scala/uncore/tilelink2/WidthWidget.scala
index 5c84b8b3..6aea2fb6 100644
--- a/src/main/scala/uncore/tilelink2/WidthWidget.scala
+++ b/src/main/scala/uncore/tilelink2/WidthWidget.scala
@@ -197,6 +197,6 @@ class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends
   }
 }
 
-class TLRAMWidthWidgetTest(little: Int, big: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMWidthWidgetTest(little: Int, big: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala
index 377198b9..c4507a8c 100644
--- a/src/main/scala/uncore/tilelink2/Xbar.scala
+++ b/src/main/scala/uncore/tilelink2/Xbar.scala
@@ -230,7 +230,7 @@ class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMXbarTest(nManagers: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMXbarTest(nManagers: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLRAMXbar(nManagers)).module).io.finished
 }
 
@@ -253,6 +253,6 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) e
   }
 }
 
-class TLMulticlientXbarTest(nManagers: Int, nClients: Int)(implicit p: Parameters) extends UnitTest(timeout = 5000000) {
+class TLMulticlientXbarTest(nManagers: Int, nClients: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients)).module).io.finished
 }