riscv/rocket-chip
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add L2$

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It still has performance bugs but no correctness bugs AFAIK.
This commit is contained in:
Andrew Waterman
2012-07-10 05:23:29 -07:00
parent 5035374f36
commit f645fb4dd7
4 changed files with 427 additions and 18 deletions
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2
rocket/src/main/scala/fpu.scala
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@ -457,7 +457,7 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
}
val rec_s = hardfloat.floatNToRecodedFloatN(load_wb_data, 23, 9)
val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12)
val sp_msbs = Fill(32, UFix(1,1))
val sp_msbs = Fix(-1, 32)
val load_wb_data_recoded = Mux(load_wb_single, Cat(sp_msbs, rec_s), rec_d)
val fsr_rm = Reg() { Bits(width = 3) }