riscv/rocket-chip
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changes after the module uniquify bug fix

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This commit is contained in:
Yunsup Lee 2012-02-29 22:00:36 -08:00
parent 813ffcbf3e
commit f641b44fb8
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/cpu.scala
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@ -37,7 +37,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
{
vu = new vu()
// cpu, vector prefetch, and vector use the DTLB
val dtlbarb = new rArbiter(3)({new ioDTLB_CPU_req()})
val dtlbarb = new hwacha.Arbiter(3)({new ioDTLB_CPU_req()})
val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3)))
when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }