riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

allow groundtest to use non-blocking DCache

Browse Source
This commit is contained in:
Howard Mao 2016-07-07 18:59:09 -07:00
parent 67871654dd
commit f62c74b82a
1 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
groundtest/src/main/scala/tile.scala
View File

@ -92,7 +92,9 @@ class GroundTestTile(id: Int, resetSignal: Bool)
val memPorts = ListBuffer.empty ++= test.io.mem
if (nCached > 0) {
val dcache = Module(new HellaCache()(dcacheParams))
val dcache_io =
if (p(NMSHRs) == 0) Module(new DCache()(dcacheParams)).io
else Module(new HellaCache()(dcacheParams)).io
val dcacheArb = Module(new HellaCacheArbiter(nCached)(dcacheParams))
dcacheArb.io.requestor.zip(test.io.cache).foreach {
@ -101,13 +103,13 @@ class GroundTestTile(id: Int, resetSignal: Bool)
dcacheIF.io.requestor <> cache
requestor <> dcacheIF.io.cache
}
dcache.io.cpu <> dcacheArb.io.mem
io.cached.head <> dcache.io.mem
dcache_io.cpu <> dcacheArb.io.mem
io.cached.head <> dcache_io.mem
// SimpleHellaCacheIF leaves invalidate_lr dangling, so we wire it to false
dcache.io.cpu.invalidate_lr := Bool(false)
dcache_io.cpu.invalidate_lr := Bool(false)
ptwPorts += dcache.io.ptw
ptwPorts += dcache_io.ptw
}
// Only Tile 0 needs to write tohost