diff --git a/uncore/src/main/scala/debug.scala b/uncore/src/main/scala/debug.scala
index daa86b82..a065d442 100644
--- a/uncore/src/main/scala/debug.scala
+++ b/uncore/src/main/scala/debug.scala
@@ -64,46 +64,56 @@ object DsbBusConsts {
   def sbAddrWidth = 12
   def sbIdWidth   = 10 
 
-  //These are the default ROM contents, which support
-  //RV32 and RV64. RV128 are implemented as NOP.
+  //These are the default ROM contents, which support RV32 and RV64.
   // See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
-  // The code assumes 4*0xF bytes of Debug RAM.
+  // The code assumes 64 bytes of Debug RAM.
 
   def defaultRomContents : Array[Byte] = Array(
-    0x6f, 0x00, 0x00, 0x06, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
+    0x6f, 0x00, 0xc0, 0x04, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
     0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
     0xf3, 0x24, 0x00, 0xf1, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x24, 0xc0, 0x43,
-    0x6f, 0x00, 0x80, 0x01, 0x93, 0x94, 0x14, 0x00, 0x63, 0xc6, 0x04, 0x00,
-    0x83, 0x34, 0x80, 0x43, 0x6f, 0x00, 0x80, 0x00, 0x13, 0x00, 0x00, 0x00,
-    0x23, 0x2e, 0x80, 0x42, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10,
-    0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00, 0x63, 0x04, 0x04, 0x00,
-    0x6f, 0x00, 0x80, 0x05, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
-    0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
-    0x13, 0x04, 0x04, 0xf4, 0x63, 0x18, 0x04, 0x02, 0x0f, 0x10, 0x00, 0x00,
+    0x6f, 0x00, 0x80, 0x00, 0x83, 0x34, 0x80, 0x43, 0x23, 0x2e, 0x80, 0x42,
+    0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b,
+    0x13, 0x74, 0x84, 0x00, 0x63, 0x12, 0x04, 0x04, 0x73, 0x24, 0x20, 0x7b,
+    0x73, 0x00, 0x20, 0x7b, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b,
+    0x13, 0x74, 0x04, 0x1c, 0x13, 0x04, 0x04, 0xf4, 0x63, 0x1e, 0x04, 0x00,
     0x73, 0x24, 0x00, 0xf1, 0x63, 0x46, 0x04, 0x00, 0x23, 0x2e, 0x90, 0x42,
-    0x67, 0x00, 0x00, 0x40, 0x13, 0x14, 0x14, 0x00, 0x63, 0x46, 0x04, 0x00,
-    0x23, 0x3c, 0x90, 0x42, 0x67, 0x00, 0x00, 0x40, 0x13, 0x00, 0x00, 0x00,
-    0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
-    0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
-    0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0xdf, 0xfb).map(x => x.toByte)
+    0x67, 0x00, 0x00, 0x40, 0x23, 0x3c, 0x90, 0x42, 0x67, 0x00, 0x00, 0x40,
+    0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10, 0x73, 0x60, 0x04, 0x7b,
+    0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02, 0xe3, 0x0c, 0x04, 0xfe,
+    0x6f, 0xf0, 0x1f, 0xfd).map(_.toByte)
 
   // These ROM contents support only RV32 
   // See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
   // The code assumes only 28 bytes of Debug RAM.
 
   def xlen32OnlyRomContents : Array[Byte] = Array(
-    0x6f, 0x00, 0x00, 0x04, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
+    0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
     0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
     0x83, 0x24, 0x80, 0x41, 0x23, 0x2c, 0x80, 0x40, 0x73, 0x24, 0x40, 0xf1,
     0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
-    0x63, 0x04, 0x04, 0x00, 0x6f, 0x00, 0x80, 0x03, 0x73, 0x24, 0x20, 0x7b,
-    0x73, 0x00, 0x20, 0x7b, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b,
-    0x13, 0x74, 0x04, 0x1c, 0x13, 0x04, 0x04, 0xf4, 0x63, 0x18, 0x04, 0x00,
-    0x0f, 0x10, 0x00, 0x00, 0x23, 0x2c, 0x90, 0x40, 0x67, 0x00, 0x00, 0x40,
-    0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10, 0x73, 0x60, 0x04, 0x7b,
-    0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02, 0xe3, 0x0c, 0x04, 0xfe,
-    0x6f, 0xf0, 0xdf, 0xfd).map(x => x.toByte)
+    0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
+    0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
+    0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x2c, 0x90, 0x40,
+    0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
+    0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
+    0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
 
+  // These ROM contents support only RV64
+  // See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
+  // The code assumes 64 bytes of Debug RAM.
+
+  def xlen64OnlyRomContents : Array[Byte] = Array(
+    0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
+    0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
+    0x83, 0x34, 0x80, 0x43, 0x23, 0x2e, 0x80, 0x42, 0x73, 0x24, 0x40, 0xf1,
+    0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
+    0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
+    0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
+    0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x3c, 0x90, 0x42,
+    0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
+    0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
+    0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
 }
 
 
@@ -243,8 +253,7 @@ class DefaultDebugModuleConfig (val ncomponents : Int, val xlen:Int)
       },
       debugRomContents = xlen match {
         case 32  => Some(DsbBusConsts.xlen32OnlyRomContents)
-        case 64  => Some(DsbBusConsts.defaultRomContents)
-        case 128 => Some(DsbBusConsts.defaultRomContents)
+        case 64  => Some(DsbBusConsts.xlen64OnlyRomContents)
       },
       hasBusMaster = false,
       hasAccess128 = false,