riscv/rocket-chip
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Merge branch 'master' into async_register_crossing

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Henry Cook 2016-09-27 14:08:27 -07:00 committed by GitHub
commit f5502df6ab
1 changed files with 2 additions and 1 deletions
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src/main/scala/uncore/tilelink2/WidthWidget.scala
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@ -65,7 +65,8 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
}
val dataOut = if (edgeIn.staticHasData(in.bits) == Some(false)) UInt(0) else dataMux(size)
val maskOut = maskMux(size) & edgeOut.mask(addr_lo, size)
val maskFull = edgeOut.mask(addr_lo, size)
val maskOut = Mux(hasData, maskMux(size) & maskFull, maskFull)
in.ready := out.ready || !last
out.valid := in.valid && last