riscv/rocket-chip
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hoist HTIF_WIDTH out to consts

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Yunsup Lee 2012-07-23 17:30:04 -07:00
parent a21c355114
commit f4e3e72ad1
2 changed files with 3 additions and 3 deletions
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1
rocket/src/main/scala/consts.scala
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@ -12,6 +12,7 @@ object Constants
val MAX_THREADS = hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK val MAX_THREADS = hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK
val HTIF_WIDTH = 8
val MEM_BACKUP_WIDTH = 16 val MEM_BACKUP_WIDTH = 16
val BR_X = Bits("b????", 4) val BR_X = Bits("b????", 4)

5
rocket/src/main/scala/top.scala
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@ -89,7 +89,6 @@ class Uncore(htif_width: Int, ntiles: Int, co: CoherencePolicyWithUncached) exte
class Top extends Component class Top extends Component
{ {
val htif_width = 8
val co = if(ENABLE_SHARING) { val co = if(ENABLE_SHARING) {
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
else new MSICoherence else new MSICoherence
@ -97,9 +96,9 @@ class Top extends Component
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
else new MICoherence else new MICoherence
} }
val io = new ioTop(htif_width) val io = new ioTop(HTIF_WIDTH)
val uncore = new Uncore(htif_width, NTILES, co) val uncore = new Uncore(HTIF_WIDTH, NTILES, co)
uncore.io <> io uncore.io <> io
var error_mode = Bool(false) var error_mode = Bool(false)