move rocketchip package sources into its own subdirectory
This commit is contained in:
Howard Mao
205
src/main/scala/rocketchip/TestConfigs.scala
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205
src/main/scala/rocketchip/TestConfigs.scala
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package rocketchip
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import Chisel._
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import groundtest._
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import rocket._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices.NTiles
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import uncore.unittests._
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import junctions._
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import junctions.unittests._
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import scala.collection.mutable.LinkedHashSet
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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import scala.math.max
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import coreplex._
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import ConfigUtils._
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class WithUnitTest extends Config(
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(pname, site, here) => pname match {
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case BuildCoreplex => {
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val groundtest = if (site(XLen) == 64)
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DefaultTestSuites.groundtest64
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else
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DefaultTestSuites.groundtest32
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TestGeneration.addSuite(groundtest("p"))
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TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
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(p: Parameters) => Module(new UnitTestCoreplex(p))
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}
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case UnitTests => (testParams: Parameters) =>
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JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 0)
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case FPUKey => None
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case UseAtomics => false
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case UseCompressed => false
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case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
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case _ => throw new CDEMatchError
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})
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class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
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class WithGroundTest extends Config(
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(pname, site, here) => pname match {
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case BuildCoreplex => (p: Parameters) => Module(new GroundTestCoreplex(p))
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case TLKey("L1toL2") => {
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val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
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TileLinkParameters(
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coherencePolicy = (
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if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
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else new MESICoherence(site(L2DirectoryRepresentation))),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
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nCachingClients = site(NCachedTileLinkPorts),
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nCachelessClients = site(NExternalClients) + site(NUncachedTileLinkPorts),
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maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
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site(GroundTestKey).map(_.maxXacts))
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.reduce(max(_, _)),
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maxClientsPerPort = 1,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = 8,
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dataBits = site(CacheBlockBytes)*8)
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}
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case BuildTiles => {
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val groundtest = if (site(XLen) == 64)
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DefaultTestSuites.groundtest64
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else
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DefaultTestSuites.groundtest32
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TestGeneration.addSuite(groundtest("p"))
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TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
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(0 until site(NTiles)).map { i =>
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val tileSettings = site(GroundTestKey)(i)
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(r: Bool, p: Parameters) => {
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Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
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case TLId => "L1toL2"
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case GroundTestId => i
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case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
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case NUncachedTileLinkPorts => tileSettings.uncached
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})))
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}
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}
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}
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case FPUKey => None
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case UseAtomics => false
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case UseCompressed => false
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case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
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case _ => throw new CDEMatchError
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})
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class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
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class ComparatorConfig extends Config(
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new WithTestRAM ++ new WithComparator ++ new GroundTestConfig)
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class ComparatorL2Config extends Config(
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new WithAtomics ++ new WithPrefetches ++
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new WithL2Cache ++ new ComparatorConfig)
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class ComparatorBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new ComparatorConfig)
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class ComparatorStatelessConfig extends Config(
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new WithStatelessBridge ++ new ComparatorConfig)
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class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
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class MemtestL2Config extends Config(
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new WithL2Cache ++ new MemtestConfig)
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class MemtestBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new MemtestConfig)
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class MemtestStatelessConfig extends Config(
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new WithNGenerators(0, 1) ++ new WithStatelessBridge ++ new MemtestConfig)
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// Test ALL the things
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class FancyMemtestConfig extends Config(
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new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
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new WithSplitL2Metadata ++ new WithL2Cache ++ new GroundTestConfig)
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class CacheFillTestConfig extends Config(
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new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig)
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class BroadcastRegressionTestConfig extends Config(
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new WithBroadcastRegressionTest ++ new GroundTestConfig)
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class BufferlessRegressionTestConfig extends Config(
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new WithBufferlessBroadcastHub ++ new BroadcastRegressionTestConfig)
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class CacheRegressionTestConfig extends Config(
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new WithCacheRegressionTest ++ new WithL2Cache ++ new GroundTestConfig)
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class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
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class FancyNastiConverterTestConfig extends Config(
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new WithNCores(2) ++ new WithNastiConverterTest ++
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
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new WithL2Cache ++ new GroundTestConfig)
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class TraceGenConfig extends Config(
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new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)
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class TraceGenBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new TraceGenConfig)
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class TraceGenL2Config extends Config(
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new WithNL2Ways(1) ++ new WithL2Capacity(32 * 64 / 1024) ++
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new WithL2Cache ++ new TraceGenConfig)
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class MIF128BitComparatorConfig extends Config(
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new WithMIFDataBits(128) ++ new ComparatorConfig)
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class MIF128BitMemtestConfig extends Config(
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new WithMIFDataBits(128) ++ new MemtestConfig)
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class MIF32BitComparatorConfig extends Config(
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new WithMIFDataBits(32) ++ new ComparatorConfig)
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class MIF32BitMemtestConfig extends Config(
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new WithMIFDataBits(32) ++ new MemtestConfig)
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class PCIeMockupTestConfig extends Config(
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new WithPCIeMockupTest ++ new GroundTestConfig)
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class WithDirectGroundTest extends Config(
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(pname, site, here) => pname match {
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case ExportGroundTestStatus => true
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case BuildCoreplex => (p: Parameters) => Module(new DirectGroundTestCoreplex(p))
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case ExtraCoreplexPorts => (p: Parameters) =>
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if (p(ExportGroundTestStatus)) new GroundTestStatus else new Bundle
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case ExtraTopPorts => (p: Parameters) =>
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if (p(ExportGroundTestStatus)) new GroundTestStatus else new Bundle
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case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
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maxClientXacts = site(GroundTestKey)(0).maxXacts,
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maxClientsPerPort = site(NBanksPerMemoryChannel),
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dataBeats = site(MIFDataBeats))
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case NBanksPerMemoryChannel => site(GroundTestKey)(0).uncached
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case _ => throw new CDEMatchError
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})
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class DirectGroundTestConfig extends Config(
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new WithDirectGroundTest ++ new GroundTestConfig)
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class DirectMemtestConfig extends Config(
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new WithDirectMemtest ++ new DirectGroundTestConfig)
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class DirectComparatorConfig extends Config(
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new WithDirectComparator ++ new DirectGroundTestConfig)
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class DirectMemtestFPGAConfig extends Config(
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new FPGAConfig ++ new DirectMemtestConfig)
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class DirectComparatorFPGAConfig extends Config(
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new FPGAConfig ++ new DirectComparatorConfig)
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class WithBusMasterTest extends Config(
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(pname, site, here) => pname match {
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case GroundTestKey => Seq.fill(site(NTiles)) {
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GroundTestTileSettings(uncached = 1)
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}
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case BuildGroundTest =>
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(p: Parameters) => Module(new BusMasterTest()(p))
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case ExtraDevices => {
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class BusMasterDevice extends Device {
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def hasClientPort = true
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def hasMMIOPort = true
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def builder(
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mmioPort: Option[ClientUncachedTileLinkIO],
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clientPort: Option[ClientUncachedTileLinkIO],
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extra: Bundle, p: Parameters) {
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val busmaster = Module(new ExampleBusMaster()(p))
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busmaster.io.mmio <> mmioPort.get
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clientPort.get <> busmaster.io.mem
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}
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override def addrMapEntry =
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AddrMapEntry("busmaster", MemSize(4096, MemAttr(AddrMapProt.RW)))
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}
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Seq(new BusMasterDevice)
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}
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case _ => throw new CDEMatchError
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})
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class BusMasterTestConfig extends Config(new WithBusMasterTest ++ new GroundTestConfig)
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