move rocketchip package sources into its own subdirectory
This commit is contained in:
Howard Mao
280
src/main/scala/rocketchip/Configs.scala
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280
src/main/scala/rocketchip/Configs.scala
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import junctions._
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import rocket._
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import uncore.agents._
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import uncore.tilelink._
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import uncore.devices._
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import uncore.converters._
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import coreplex._
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import scala.math.max
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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class BasePlatformConfig extends Config (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val internalIOAddrMap: AddrMap = {
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
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entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
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new AddrMap(entries)
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}
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lazy val externalAddrMap = new AddrMap(
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site(ExtIOAddrMapEntries),
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start = BigInt("50000000", 16),
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collapse = true)
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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val memSize = site(ExtMemSize)
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val intern = AddrMapEntry("int", internalIOAddrMap)
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val extern = AddrMapEntry("ext", externalAddrMap)
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val ioMap = if (site(ExportMMIOPort)) AddrMap(intern, extern) else AddrMap(intern)
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val addrMap = AddrMap(
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AddrMapEntry("io", ioMap),
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AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
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Dump("MEM_BASE", addrMap("mem").start)
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addrMap
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}
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def makeConfigString() = {
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val addrMap = globalAddrMap
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val plicAddr = addrMap("io:int:plic").start
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val prciAddr = addrMap("io:int:prci").start
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val plicInfo = site(PLICKey)
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val xLen = site(XLen)
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val res = new StringBuilder
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + plicInfo.pendingBase).toString(16)};\n"
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res append s" ndevs ${plicInfo.nDevices};\n"
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res append "};\n"
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res append "rtc {\n"
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res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
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res append "};\n"
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res append "ram {\n"
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res append " 0 {\n"
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res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
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res append s" size 0x${addrMap("mem").size.toString(16)};\n"
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res append " };\n"
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res append "};\n"
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res append "core {\n"
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for (i <- 0 until site(NTiles)) {
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val isa = s"rv${site(XLen)}im${if (site(UseAtomics)) "a" else ""}${if (site(FPUKey).nonEmpty) "fd" else ""}"
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa $isa;\n"
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res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
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res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
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res append s" plic {\n"
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res append s" m {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n"
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res append s" };\n"
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if (site(UseVM)) {
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res append s" s {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
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res append s" };\n"
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}
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res append s" };\n"
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res append " };\n"
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res append " };\n"
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}
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res append "};\n"
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for (device <- site(ExtraDevices)) {
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if (device.hasMMIOPort) {
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val deviceName = device.addrMapEntry.name
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val deviceRegion = addrMap("io:ext:" + deviceName)
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res.append(device.makeConfigString(deviceRegion))
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}
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}
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res append '\u0000'
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res.toString.getBytes
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}
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lazy val innerDataBits = 64
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
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case NExtInterrupts => 2
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case AsyncDebugBus => false
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case AsyncMMIOChannels => false
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case ExtraDevices => Nil
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case ExtraTopPorts => (p: Parameters) => new Bundle
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case ExtMMIOPorts => Nil
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case ExtIOAddrMapEntries =>
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site(ExtraDevices)
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.filter(_.hasMMIOPort)
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.map(_.addrMapEntry) ++
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site(ExtMMIOPorts)
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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case ExportMMIOPort => (site(ExtraDevices).filter(_.hasMMIOPort).size + site(ExtMMIOPorts).size) > 0
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case NExternalClients => (if (site(NExtBusAXIChannels) > 1) 1 else 0) +
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site(ExtraDevices).filter(_.hasClientPort).size
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case ConnectExtraPorts =>
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(out: Bundle, in: Bundle, p: Parameters) => out <> in
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(XLen))
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case ConfigString => makeConfigString()
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case GlobalAddrMap => globalAddrMap
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case _ => throw new CDEMatchError
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}})
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class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
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class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
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class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
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class DefaultBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new BaseConfig)
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class FPGAConfig extends Config (
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(pname,site,here) => pname match {
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case NAcquireTransactors => 4
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case ExportGroundTestStatus => true
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case _ => throw new CDEMatchError
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}
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)
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class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
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class DefaultL2FPGAConfig extends Config(
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new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
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class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
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class WithNMemoryChannels(n: Int) extends Config(
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(pname,site,here) => pname match {
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case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
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case _ => throw new CDEMatchError
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}
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)
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class WithExtMemSize(n: Long) extends Config(
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(pname,site,here) => pname match {
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case ExtMemSize => Dump("MEM_SIZE", n)
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case _ => throw new CDEMatchError
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}
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)
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class WithAHB extends Config(
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(pname, site, here) => pname match {
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case TMemoryChannels => BusType.AHB
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case NExtMMIOAHBChannels => 1
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})
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class WithTL extends Config(
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(pname, site, here) => pname match {
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case TMemoryChannels => BusType.TL
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case NExtMMIOTLChannels => 1
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})
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class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
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class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
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class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultSmallConfig)
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class DualBankConfig extends Config(
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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class DualBankL2Config extends Config(
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new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
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class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
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class DualChannelL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithL2Cache ++ new BaseConfig)
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class DualChannelDualBankConfig extends Config(
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new WithNMemoryChannels(2) ++
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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class DualChannelDualBankL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
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new WithL2Cache ++ new BaseConfig)
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class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
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class WithMIFDataBits(n: Int) extends Config(
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(pname, site, here) => pname match {
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case MIFDataBits => Dump("MIF_DATA_BITS", n)
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})
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class MIF128BitConfig extends Config(
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new WithMIFDataBits(128) ++ new BaseConfig)
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class MIF32BitConfig extends Config(
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new WithMIFDataBits(32) ++ new BaseConfig)
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class SmallL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
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new WithL2Capacity(256) ++ new DefaultL2Config)
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class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity(256) ++ new DefaultL2Config)
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class DualChannelBenchmarkConfig extends Config(new WithNMemoryChannels(2) ++ new SingleChannelBenchmarkConfig)
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class QuadChannelBenchmarkConfig extends Config(new WithNMemoryChannels(4) ++ new SingleChannelBenchmarkConfig)
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class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ new SingleChannelBenchmarkConfig)
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class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
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class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
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class DualCoreConfig extends Config(
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new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
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class TinyConfig extends Config(
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new WithRV32 ++ new WithSmallCores ++
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new WithStatelessBridge ++ new BaseConfig)
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class WithTestRAM extends Config(
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(pname, site, here) => pname match {
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case ExtraDevices => {
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class TestRAMDevice extends Device {
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val ramSize = 0x1000
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def hasClientPort = false
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def hasMMIOPort = true
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def builder(
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mmioPort: Option[ClientUncachedTileLinkIO],
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clientPort: Option[ClientUncachedTileLinkIO],
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extra: Bundle, p: Parameters) {
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val testram = Module(new TileLinkTestRAM(ramSize)(p))
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testram.io <> mmioPort.get
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}
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override def addrMapEntry =
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AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW)))
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}
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Seq(new TestRAMDevice)
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}
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})
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