Fix I$ miss perfctr
The old version was counting prefetches, too.
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1be1433f04
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@ -285,7 +285,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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io.cpu.resp <> fq.io.deq
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io.cpu.resp <> fq.io.deq
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// performance events
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// performance events
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io.cpu.perf.acquire := edge.done(icache.io.tl_out(0).a)
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io.cpu.perf := icache.io.perf
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io.cpu.perf.tlbMiss := io.ptw.req.fire()
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io.cpu.perf.tlbMiss := io.ptw.req.fire()
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def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1))
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def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1))
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@ -68,6 +68,10 @@ class ICacheResp(outer: ICache) extends Bundle {
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override def cloneType = new ICacheResp(outer).asInstanceOf[this.type]
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override def cloneType = new ICacheResp(outer).asInstanceOf[this.type]
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}
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}
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class ICachePerfEvents extends Bundle {
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val acquire = Bool()
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}
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class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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val hartid = UInt(INPUT, hartIdLen)
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val hartid = UInt(INPUT, hartIdLen)
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val req = Decoupled(new ICacheReq).flip
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val req = Decoupled(new ICacheReq).flip
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@ -81,6 +85,8 @@ class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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val invalidate = Bool(INPUT)
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val invalidate = Bool(INPUT)
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val tl_out = outer.masterNode.bundleOut
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val tl_out = outer.masterNode.bundleOut
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val tl_in = outer.slaveNode.map(_.bundleIn)
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val tl_in = outer.slaveNode.map(_.bundleIn)
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val perf = new ICachePerfEvents().asOutput
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}
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}
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// get a tile-specific property without breaking deduplication
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// get a tile-specific property without breaking deduplication
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@ -343,4 +349,6 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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when (!refill_valid) { invalidated := false.B }
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when (!refill_valid) { invalidated := false.B }
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when (refill_fire) { refill_valid := true.B }
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when (refill_fire) { refill_valid := true.B }
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when (refill_done) { refill_valid := false.B}
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when (refill_done) { refill_valid := false.B}
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io.perf.acquire := refill_fire
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}
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}
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