riscv/rocket-chip
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vvcfgivl and vsetvl works

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Yunsup Lee committed 2012-02-09 02:35:21 -08:00
1 parent 92493ad153
commit f47d888feb
5 files changed
+59 -55
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rocket/src/main/scala/consts.scala
-1
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@@ -66,7 +66,6 @@ object Constants
val WB_ALU = UFix(2, 3);
val WB_TSC = UFix(4, 3);
val WB_IRT = UFix(5, 3);
val WB_VEC = UFix(6, 3);
val N = UFix(0, 1);
val Y = UFix(1, 1);