riscv/rocket-chip
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Update to privileged architecture 1.7

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Andrew Waterman
2015-05-18 18:23:58 -07:00
parent 254498042a
commit f460cb6c54
7 changed files with 249 additions and 161 deletions
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rocket/src/main/scala/util.scala
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@ -12,6 +12,9 @@ object Util {
implicit def intSeqToUIntSeq(x: Iterable[Int]): Iterable[UInt] = x.map(UInt(_))
implicit def seqToVec[T <: Data](x: Iterable[T]): Vec[T] = Vec(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit def sextToConv(x: UInt) = new AnyRef {
def sextTo(n: Int): UInt = Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
implicit def intToUnsigned(x: Int): Unsigned = new Unsigned(x)
implicit def booleanToIntConv(x: Boolean) = new AnyRef {