riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Update to privileged architecture 1.7

Browse Source
This commit is contained in:
Andrew Waterman
2015-05-18 18:23:58 -07:00
parent 254498042a
commit f460cb6c54
7 changed files with 249 additions and 161 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/tlb.scala
View File

@ -146,7 +146,7 @@ class TLB extends TLBModule {
val plru = new PseudoLRU(entries)
val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace)
val priv = Mux(io.ptw.status.prv === PRV_M && !io.req.bits.instruction, io.ptw.status.mprv, io.ptw.status.prv)
val priv = Mux(io.ptw.status.mprv && !io.req.bits.instruction, io.ptw.status.prv1, io.ptw.status.prv)
val priv_s = priv === PRV_S
val priv_uses_vm = priv <= PRV_S
val req_xwr = Cat(!r_req.store, r_req.store, !(r_req.instruction || r_req.store))
@ -155,7 +155,7 @@ class TLB extends TLBModule {
val w_array = Mux(priv_s, sw_array, uw_array)
val x_array = Mux(priv_s, sx_array, ux_array)
val vm_enabled = io.ptw.status.vm(2) && priv_uses_vm
val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm
val bad_va = io.req.bits.vpn(vpnBits) != io.req.bits.vpn(vpnBits-1)
// it's only a store hit if the dirty bit is set
val tag_hits = tag_cam.io.hits & (dirty_array | ~(io.req.bits.store.toSInt & w_array))