From f4524e4c91e708e80e6d6df36941b71169748687 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 29 Aug 2016 15:56:28 -0700 Subject: [PATCH] Add PML for Boolean.option; use it --- src/main/scala/coreplex/Coreplex.scala | 6 +++--- src/main/scala/rocket/rocket.scala | 14 ++++++------ src/main/scala/rocket/util.scala | 5 ++++- src/main/scala/rocketchip/RocketChip.scala | 25 +++++++++++----------- 4 files changed, 27 insertions(+), 23 deletions(-) diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index 8599205e..cab70059 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -70,7 +70,7 @@ class Uncore(implicit val p: Parameters) extends Module val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip val ext_uncached = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip val prci = Vec(nTiles, new PRCITileIO).asOutput - val mmio = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None + val mmio = exportMMIO.option(new ClientUncachedTileLinkIO()(outermostMMIOParams)) val interrupts = Vec(p(NExtInterrupts), Bool()).asInput val debug = new DebugBusIO()(p).flip } @@ -234,11 +234,11 @@ abstract class Coreplex(implicit val p: Parameters) extends Module class CoreplexIO(implicit val p: Parameters) extends Bundle { val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)) val ext_clients = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip - val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None + val mmio = p(ExportMMIOPort).option(new ClientUncachedTileLinkIO()(outermostMMIOParams)) val interrupts = Vec(p(NExtInterrupts), Bool()).asInput val debug = new DebugBusIO()(p).flip val extra = p(ExtraCoreplexPorts)(p) - val success: Option[Bool] = if (hasSuccessFlag) Some(Bool(OUTPUT)) else None + val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT)) } def hasSuccessFlag: Boolean = false diff --git a/src/main/scala/rocket/rocket.scala b/src/main/scala/rocket/rocket.scala index bcf31b34..4c71c4c5 100644 --- a/src/main/scala/rocket/rocket.scala +++ b/src/main/scala/rocket/rocket.scala @@ -145,13 +145,13 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) { } val decode_table = { - (if (usingMulDiv) new MDecode +: (if (xLen > 32) Seq(new M64Decode) else Nil) else Nil) ++: - (if (usingAtomics) new ADecode +: (if (xLen > 32) Seq(new A64Decode) else Nil) else Nil) ++: - (if (usingFPU) new FDecode +: (if (xLen > 32) Seq(new F64Decode) else Nil) else Nil) ++: - (if (usingRoCC) Some(new RoCCDecode) else None) ++: - (if (xLen > 32) Some(new I64Decode) else None) ++: - (if (usingVM) Some(new SDecode) else None) ++: - (if (usingDebug) Some(new DebugDecode) else None) ++: + (if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++: + (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: + (if (usingFPU) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: + (usingRoCC.option(new RoCCDecode)) ++: + ((xLen > 32).option(new I64Decode)) ++: + (usingVM.option(new SDecode)) ++: + (usingDebug.option(new DebugDecode)) ++: Seq(new IDecode) } flatMap(_.table) diff --git a/src/main/scala/rocket/util.scala b/src/main/scala/rocket/util.scala index f701dbeb..54eaf6e3 100644 --- a/src/main/scala/rocket/util.scala +++ b/src/main/scala/rocket/util.scala @@ -26,8 +26,11 @@ object Util { } } - implicit def booleanToIntConv(x: Boolean) = new AnyRef { + implicit class BooleanToAugmentedBoolean(val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 + + // this one's snagged from scalaz + def option[T](z: T): Option[T] = if (x) Some(z) else None } } diff --git a/src/main/scala/rocketchip/RocketChip.scala b/src/main/scala/rocketchip/RocketChip.scala index 6f0ae1eb..2bbf84b6 100644 --- a/src/main/scala/rocketchip/RocketChip.scala +++ b/src/main/scala/rocketchip/RocketChip.scala @@ -8,6 +8,7 @@ import junctions._ import uncore.tilelink._ import uncore.devices._ import uncore.util._ +import rocket.Util._ import uncore.converters._ import uncore.coherence.{InnerTLId, OuterTLId} import rocket._ @@ -79,24 +80,24 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasTopLevelParameters class TopIO(implicit p: Parameters) extends BasicTopIO()(p) { - val mem_clk = if (p(AsyncMemChannels)) Some(Vec(nMemChannels, Clock(INPUT))) else None - val mem_rst = if (p(AsyncMemChannels)) Some(Vec(nMemChannels, Bool (INPUT))) else None + val mem_clk = p(AsyncMemChannels).option(Vec(nMemChannels, Clock(INPUT))) + val mem_rst = p(AsyncMemChannels).option(Vec(nMemChannels, Bool (INPUT))) val mem_axi = Vec(nMemAXIChannels, new NastiIO) val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO) val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams)) val interrupts = Vec(p(NExtTopInterrupts), Bool()).asInput - val bus_clk = if (p(AsyncBusChannels)) Some(Vec(p(NExtBusAXIChannels), Clock(INPUT))) else None - val bus_rst = if (p(AsyncBusChannels)) Some(Vec(p(NExtBusAXIChannels), Bool (INPUT))) else None + val bus_clk = p(AsyncBusChannels).option(Vec(p(NExtBusAXIChannels), Clock(INPUT))) + val bus_rst = p(AsyncBusChannels).option(Vec(p(NExtBusAXIChannels), Bool (INPUT))) val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip - val mmio_clk = if (p(AsyncMMIOChannels)) Some(Vec(p(NExtMMIOAXIChannels), Clock(INPUT))) else None - val mmio_rst = if (p(AsyncMMIOChannels)) Some(Vec(p(NExtMMIOAXIChannels), Bool (INPUT))) else None + val mmio_clk = p(AsyncMMIOChannels).option(Vec(p(NExtMMIOAXIChannels), Clock(INPUT))) + val mmio_rst = p(AsyncMMIOChannels).option(Vec(p(NExtMMIOAXIChannels), Bool (INPUT))) val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO) val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO) val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams)) - val debug_clk = if (p(AsyncDebugBus) & !p(IncludeJtagDTM)) Some(Clock(INPUT)) else None - val debug_rst = if (p(AsyncDebugBus) & !p(IncludeJtagDTM)) Some(Bool(INPUT)) else None - val debug = if (!p(IncludeJtagDTM)) Some(new DebugBusIO()(p).flip) else None - val jtag = if ( p(IncludeJtagDTM)) Some(new JtagIO(true).flip) else None + val debug_clk = (p(AsyncDebugBus) && !p(IncludeJtagDTM)).option(Clock(INPUT)) + val debug_rst = (p(AsyncDebugBus) && !p(IncludeJtagDTM)).option(Bool(INPUT)) + val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO()(p).flip) + val jtag = p(IncludeJtagDTM).option(new JtagIO(true).flip) val extra = p(ExtraTopPorts)(p) } @@ -136,7 +137,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters { val periphery = Module(new Periphery()(innerParams)) val io = new TopIO { - val success = if (coreplex.hasSuccessFlag) Some(Bool(OUTPUT)) else None + val success = coreplex.hasSuccessFlag.option(Bool(OUTPUT)) } io.success zip coreplex.io.success map { case (x, y) => x := y } @@ -201,7 +202,7 @@ class Periphery(implicit val p: Parameters) extends Module val io = new Bundle { val mem_in = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)).flip val clients_out = Vec(p(NExternalClients), new ClientUncachedTileLinkIO()(innerParams)) - val mmio_in = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams).flip) else None + val mmio_in = exportMMIO.option(new ClientUncachedTileLinkIO()(outermostMMIOParams).flip) val mem_axi = Vec(nMemAXIChannels, new NastiIO) val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO) val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))