riscv/rocket-chip
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rename M_FENCE to M_NOP

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Yunsup Lee 2013-10-28 22:37:41 -07:00
parent 42693d43ad
commit f440df5338
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/consts.scala
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@ -22,7 +22,7 @@ trait MemoryOpConstants {
val M_PFR = Bits("b00010"); // prefetch with intent to read val M_PFR = Bits("b00010"); // prefetch with intent to read
val M_PFW = Bits("b00011"); // prefetch with intent to write val M_PFW = Bits("b00011"); // prefetch with intent to write
val M_XA_SWAP = Bits("b00100"); val M_XA_SWAP = Bits("b00100");
val M_FENCE = Bits("b00101"); // memory fence val M_NOP = Bits("b00101");
val M_XLR = Bits("b00110"); val M_XLR = Bits("b00110");
val M_XSC = Bits("b00111"); val M_XSC = Bits("b00111");
val M_XA_ADD = Bits("b01000"); val M_XA_ADD = Bits("b01000");