riscv/rocket-chip
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pass nMemChannels to coreplex through CoreplexConfig

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Howard Mao
2016-09-12 12:40:10 -07:00
parent 9d9f90646d
commit f3cdeb08c6
3 changed files with 8 additions and 7 deletions
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3
src/main/scala/rocketchip/Top.scala
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@ -16,6 +16,8 @@ import coreplex._
case object GlobalAddrMap extends Field[GlobalVariable[AddrMap]]
case object ConfigString extends Field[GlobalVariable[String]]
case object NCoreplexExtClients extends Field[GlobalVariable[Int]]
/** Function for building Coreplex */
case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
/** Base Top with no Periphery */
abstract class BaseTop(val p: Parameters) extends LazyModule {
@ -36,6 +38,7 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
nTiles = p(NTiles),
nExtInterrupts = outer.pInterrupts.sum,
nSlaves = outer.pBusMasters.sum,
nMemChannels = p(NMemoryChannels),
hasSupervisor = p(UseVM),
hasExtMMIOPort = !(outer.pDevices.get.isEmpty && p(ExtMMIOPorts).isEmpty)
)