riscv/rocket-chip
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ahb: AHB parameters should be site specific

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Conflicts:
	src/main/scala/Configs.scala
This commit is contained in:
Wesley W. Terpstra 2016-05-24 15:59:59 -07:00 committed by Andrew Waterman
parent 172c4f25f4
commit f3a557b67b
1 changed files with 5 additions and 4 deletions
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9
src/main/scala/Configs.scala
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@ -133,9 +133,6 @@ class BaseConfig extends Config (
addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)), addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
idBits = Dump("MEM_ID_BITS", site(MIFTagBits))) idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
} }
case HastiKey => HastiParameters(
dataBits = site(XLen),
addrBits = site(PAddrBits))
//Params used by all caches //Params used by all caches
case NSets => findBy(CacheName) case NSets => findBy(CacheName)
case NWays => findBy(CacheName) case NWays => findBy(CacheName)
@ -239,11 +236,15 @@ class BaseConfig extends Config (
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) + case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
log2Up(site(TLKey(site(TLId))).nClients) log2Up(site(TLKey(site(TLId))).nClients)
case ExtraL1Clients => 1 // HTIF // TODO not really a parameter case ExtraL1Clients => 1 // HTIF // TODO not really a parameter
case HastiId => "TL" case HastiId => "Ext"
case HastiKey("TL") => case HastiKey("TL") =>
HastiParameters( HastiParameters(
addrBits = site(PAddrBits), addrBits = site(PAddrBits),
dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats) dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
case HastiKey("Ext") =>
HastiParameters(
addrBits = site(PAddrBits),
dataBits = site(XLen))
case TLKey("L1toL2") => case TLKey("L1toL2") =>
TileLinkParameters( TileLinkParameters(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)), coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),