riscv/rocket-chip
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Add some covers for L1 memory system

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This commit is contained in:
Andrew Waterman
2017-10-09 18:33:36 -07:00
parent 0e6aa7ae9d
commit f3825270c1
4 changed files with 67 additions and 4 deletions
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18
src/main/scala/rocket/ICache.scala
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@ -11,6 +11,8 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import chisel3.internal.sourceinfo.SourceInfo
case class ICacheParams(
nSets: Int = 64,
@ -326,6 +328,11 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
tl.b.valid := false
tl.c.ready := true
tl.e.ready := true
ccover(s0_valid && s1_slaveValid, "CONCURRENT_ITIM_ACCESS_1", "ITIM accessed, then I$ accessed next cycle")
ccover(s0_valid && s2_slaveValid, "CONCURRENT_ITIM_ACCESS_2", "ITIM accessed, then I$ accessed two cycles later")
ccover(tl.d.valid && !tl.d.ready, "ITIM_D_STALL", "ITIM response blocked by D-channel")
ccover(tl_out.d.valid && !tl_out.d.ready, "ITIM_BLOCK_D", "D-channel blocked by ITIM access")
}
}
@ -358,6 +365,11 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
lgSize = lgCacheBlockBytes,
param = TLHints.PREFETCH_READ)._2
}
ccover(send_hint && !tl_out.a.ready, "PREFETCH_A_STALL", "I$ prefetch blocked by A-channel")
ccover(refill_valid && (tl_out.d.fire() && !refill_one_beat), "PREFETCH_D_BEFORE_MISS_D", "I$ prefetch resolves before miss")
ccover(!refill_valid && (tl_out.d.fire() && !refill_one_beat), "PREFETCH_D_AFTER_MISS_D", "I$ prefetch resolves after miss")
ccover(tl_out.a.fire() && hint_outstanding, "PREFETCH_D_AFTER_MISS_A", "I$ prefetch resolves after second miss")
}
tl_out.b.ready := Bool(true)
tl_out.c.valid := Bool(false)
@ -369,4 +381,10 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
when (refill_done) { refill_valid := false.B}
io.perf.acquire := refill_fire
ccover(!send_hint && (tl_out.a.valid && !tl_out.a.ready), "MISS_A_STALL", "I$ miss blocked by A-channel")
ccover(invalidate && refill_valid, "FLUSH_DURING_MISS", "I$ flushed during miss")
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, s"ICACHE_$label", "MemorySystem;;" + desc)
}