riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

TLROM: use the smallest ROM implementation that works

Browse Source 
The contents everywhere else are still zero.
This commit is contained in:
Wesley W. Terpstra 2017-03-24 16:07:59 -07:00
parent ac205ca10a
commit f36b1766f8
1 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/uncore/devices/Rom.scala
View File

@ -30,20 +30,22 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
} }
val contents = contentsDelayed val contents = contentsDelayed
require (contents.size <= size) val wrapSize = 1 << log2Ceil(contents.size)
require (wrapSize <= size)
val in = io.in(0) val in = io.in(0)
val edge = node.edgesIn(0) val edge = node.edgesIn(0)
val words = (contents ++ Seq.fill(size-contents.size)(0.toByte)).grouped(beatBytes).toSeq val words = (contents ++ Seq.fill(wrapSize-contents.size)(0.toByte)).grouped(beatBytes).toSeq
val bigs = words.map(_.foldRight(BigInt(0)){ case (x,y) => (x.toInt & 0xff) | y << 8}) val bigs = words.map(_.foldRight(BigInt(0)){ case (x,y) => (x.toInt & 0xff) | y << 8})
val rom = Vec(bigs.map(x => UInt(x, width = 8*beatBytes))) val rom = Vec(bigs.map(x => UInt(x, width = 8*beatBytes)))
in.d.valid := in.a.valid in.d.valid := in.a.valid
in.a.ready := in.d.ready in.a.ready := in.d.ready
val index = in.a.bits.address(log2Ceil(size)-1,log2Ceil(beatBytes)) val index = in.a.bits.address(log2Ceil(wrapSize)-1,log2Ceil(beatBytes))
in.d.bits := edge.AccessAck(in.a.bits, UInt(0), rom(index)) val high = if (wrapSize == size) UInt(0) else in.a.bits.address(log2Ceil(size)-1, log2Ceil(wrapSize))
in.d.bits := edge.AccessAck(in.a.bits, UInt(0), Mux(high.orR, UInt(0), rom(index)))
// Tie off unused channels // Tie off unused channels
in.b.valid := Bool(false) in.b.valid := Bool(false)