riscv/rocket-chip
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tile: bus blocker needs to know width :(

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This commit is contained in:
Henry Cook 2017-11-17 20:17:17 -08:00
parent b625e68360
commit f3575404c0
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -6,7 +6,7 @@ import Chisel._
import Chisel.ImplicitConversions._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.coreplex.{CacheBlockBytes, SystemBusKey}
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
@ -99,6 +99,7 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics:
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
val module: CanHaveScratchpadModule
val cacheBlockBytes = p(CacheBlockBytes)
val masterPortBeatBytes = p(SystemBusKey).beatBytes
val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)))
@ -113,7 +114,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
val tile_master_blocker =
tileParams.blockerCtrlAddr
.map(BasicBusBlockerParams(_, xBytes, deadlock = true))
.map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
.map(bp => LazyModule(new BasicBusBlocker(bp)))
masterNode := tile_master_blocker.map { _.node := tileBus.node } getOrElse { tileBus.node }