riscv/rocket-chip
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make sure L2 tracker doesn't read data array again if data buffer already filled

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This commit is contained in:
Howard Mao 2016-07-29 16:47:31 -07:00
parent 2891eb879a
commit f34b0b0447
2 changed files with 18 additions and 13 deletions
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14
uncore/src/main/scala/agents/Cache.scala
View File

@ -612,9 +612,8 @@ trait ReadsFromOuterCacheDataArray extends HasCoherenceMetadataBuffer
can_update_pending: Bool = Bool(true)) { can_update_pending: Bool = Bool(true)) {
val port = io.data val port = io.data
when (can_update_pending) { when (can_update_pending) {
pending_reads := (pending_reads & pending_reads := (pending_reads | add_pending_bit) &
dropPendingBit(port.read) & drop_pending_bit) | dropPendingBit(port.read) & drop_pending_bit
add_pending_bit
} }
port.read.valid := state === s_busy && pending_reads.orR && !block_pending_read port.read.valid := state === s_busy && pending_reads.orR && !block_pending_read
port.read.bits := L2DataReadReq( port.read.bits := L2DataReadReq(
@ -690,6 +689,7 @@ trait HasAMOALU extends HasAcquireMetadataBuffer
val wmask = FillInterleaved(8, wmask_buffer(beat)) val wmask = FillInterleaved(8, wmask_buffer(beat))
data_buffer(beat) := ~wmask & old_data | data_buffer(beat) := ~wmask & old_data |
wmask & Mux(xact_iacq.isAtomic(), amoalu.io.out << amo_shift_bits, new_data) wmask & Mux(xact_iacq.isAtomic(), amoalu.io.out << amo_shift_bits, new_data)
wmask_buffer(beat) := ~UInt(0, innerWriteMaskBits)
when(xact_iacq.isAtomic() && xact_addr_beat === beat) { amo_result := old_data } when(xact_iacq.isAtomic() && xact_addr_beat === beat) { amo_result := old_data }
} }
} }
@ -795,7 +795,7 @@ class CacheVoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters)
xact_old_meta.coh.outer)), xact_old_meta.coh.outer)),
s_idle) s_idle)
when(io.inner.release.fire()) { data_buffer(io.irel().addr_beat) := io.irel().data } mergeDataInner(io.inner.release)
when(irel_is_allocating) { when(irel_is_allocating) {
pending_writes := addPendingBitWhenBeatHasData(io.inner.release) pending_writes := addPendingBitWhenBeatHasData(io.inner.release)
@ -966,7 +966,10 @@ class CacheAcquireTracker(trackerId: Int)(implicit p: Parameters)
readDataArray( readDataArray(
drop_pending_bit = (dropPendingBitWhenBeatHasData(io.inner.release) & drop_pending_bit = (dropPendingBitWhenBeatHasData(io.inner.release) &
dropPendingBitWhenBeatHasData(io.outer.grant)), dropPendingBitWhenBeatHasData(io.outer.grant)),
add_pending_bit = addPendingBitWhenBeatNeedsRead(io.inner.acquire, Bool(alwaysWriteFullBeat)), add_pending_bit = addPendingBitWhenBeatNeedsRead(
io.inner.acquire,
always = Bool(alwaysWriteFullBeat),
unless = data_valid(io.iacq().addr_beat)),
block_pending_read = ognt_counter.pending, block_pending_read = ognt_counter.pending,
can_update_pending = state =/= s_idle || io.alloc.irel.should) can_update_pending = state =/= s_idle || io.alloc.irel.should)
@ -1119,7 +1122,6 @@ class L2WritebackUnit(val trackerId: Int)(implicit p: Parameters) extends XactTr
add_pending_data_bits = addPendingBitInternal(io.data.resp), add_pending_data_bits = addPendingBitInternal(io.data.resp),
add_pending_send_bit = io.meta.resp.valid && needs_outer_release) add_pending_send_bit = io.meta.resp.valid && needs_outer_release)
// Respond to the initiating transaction handler signalling completion of the writeback // Respond to the initiating transaction handler signalling completion of the writeback
io.wb.resp.valid := state === s_busy && all_pending_done io.wb.resp.valid := state === s_busy && all_pending_done
io.wb.resp.bits.id := xact_id io.wb.resp.bits.id := xact_id

17
uncore/src/main/scala/agents/Trackers.scala
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@ -105,9 +105,10 @@ trait HasPendingBitHelpers extends HasDataBeatCounters {
alloc_override: Bool = Bool(false)): UInt = alloc_override: Bool = Bool(false)): UInt =
addPendingBitWhenBeatHasData(in, in.bits.allocate() || alloc_override) addPendingBitWhenBeatHasData(in, in.bits.allocate() || alloc_override)
def addPendingBitWhenBeatNeedsRead(in: DecoupledIO[AcquireFromSrc], inc: Bool = Bool(true)): UInt = { def addPendingBitWhenBeatNeedsRead(in: DecoupledIO[AcquireFromSrc],
always: Bool = Bool(true), unless: Bool = Bool(false)): UInt = {
val a = in.bits val a = in.bits
val needs_read = (a.isGet() || a.isAtomic() || a.hasPartialWritemask()) || inc val needs_read = !unless && (a.isGet() || a.isAtomic() || a.hasPartialWritemask()) || always
addPendingBitWhenBeat(in.fire() && needs_read, a) addPendingBitWhenBeat(in.fire() && needs_read, a)
} }
@ -176,6 +177,7 @@ trait HasDataBuffer extends HasCoherenceAgentParameters {
trait HasByteWriteMaskBuffer extends HasDataBuffer { trait HasByteWriteMaskBuffer extends HasDataBuffer {
val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerWriteMaskBits))) val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerWriteMaskBits)))
val data_valid = Vec(wmask_buffer.map(wmask => wmask.andR))
override def initDataInner[T <: Acquire](in: DecoupledIO[T], alloc: Bool) { override def initDataInner[T <: Acquire](in: DecoupledIO[T], alloc: Bool) {
when(in.fire() && in.bits.hasData() && alloc) { when(in.fire() && in.bits.hasData() && alloc) {
@ -190,7 +192,8 @@ trait HasByteWriteMaskBuffer extends HasDataBuffer {
val old_data = incoming // Refilled, written back, or de-cached data val old_data = incoming // Refilled, written back, or de-cached data
val new_data = data_buffer(beat) // Newly Put data is already in the buffer val new_data = data_buffer(beat) // Newly Put data is already in the buffer
val wmask = FillInterleaved(8, wmask_buffer(beat)) val wmask = FillInterleaved(8, wmask_buffer(beat))
data_buffer(beat) := ~wmask & old_data | wmask & new_data data_buffer(beat) := (~wmask & old_data) | (wmask & new_data)
wmask_buffer(beat) := ~UInt(0, innerWriteMaskBits)
} }
def clearWmaskBuffer() { def clearWmaskBuffer() {
@ -520,10 +523,10 @@ trait AcceptsInnerAcquires extends HasAcquireMetadataBuffer
// Track which beats are ready for response // Track which beats are ready for response
when(!iacq_is_allocating) { when(!iacq_is_allocating) {
pending_ignt_data := (pending_ignt_data & dropPendingBitWhenBeatHasData(io.inner.grant)) | pending_ignt_data := pending_ignt_data |
addPendingBitWhenBeatHasData(io.inner.release) | addPendingBitWhenBeatHasData(io.inner.release) |
addPendingBitWhenBeatHasData(io.outer.grant) | addPendingBitWhenBeatHasData(io.outer.grant) |
add_pending_bits add_pending_bits
} }
if (p(EnableL2Logging)) { if (p(EnableL2Logging)) {