riscv/rocket-chip
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make sure timeout doesn't trigger spuriously on reset

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This commit is contained in:
Howard Mao
2015-11-18 22:53:50 -08:00
parent 8bc90ab9bd
commit f325874420
1 changed files with 1 additions and 1 deletions
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groundtest/src/main/scala/util.scala
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@@ -25,7 +25,7 @@ class Timer(initCount: Int) extends Module {
countdown := countdown - UInt(1) countdown := countdown - UInt(1)
} }
io.timeout := countdown === UInt(0) io.timeout := countdown === UInt(0) && active
} }
object Timer { object Timer {