diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala index 0d46300c..21ddd87f 100644 --- a/src/main/scala/uncore/tilelink2/IntNodes.scala +++ b/src/main/scala/uncore/tilelink2/IntNodes.scala @@ -60,6 +60,7 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())).flip } + def colour = "#0000ff" // blue def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { (None, () => { // Cannot use bulk connect, because the widths could differ diff --git a/src/main/scala/uncore/tilelink2/LazyModule.scala b/src/main/scala/uncore/tilelink2/LazyModule.scala index b18e0e5c..d2bb370b 100644 --- a/src/main/scala/uncore/tilelink2/LazyModule.scala +++ b/src/main/scala/uncore/tilelink2/LazyModule.scala @@ -35,7 +35,8 @@ abstract class LazyModule val buf = new StringBuilder buf ++= "\n" buf ++= "\n" - buf ++= " \n" + buf ++= " \n" + buf ++= " \n" buf ++= " \n" nodesGraphML(buf, " ") edgesGraphML(buf, " ") @@ -48,7 +49,7 @@ abstract class LazyModule private def nodesGraphML(buf: StringBuilder, pad: String) { buf ++= s"""${pad}\n""" - buf ++= s"""${pad} ${module.name}\n""" + buf ++= s"""${pad} ${module.name}\n""" buf ++= s"""${pad} \n""" nodes.filter(!_.omitGraphML).foreach { n => buf ++= s"""${pad} \n""" @@ -62,7 +63,7 @@ abstract class LazyModule buf ++= pad buf ++= "\n""" + buf ++= s""" target=\"${o.lazyModule.index}::${o.index}\">\n""" } } children.filter(!_.omitGraphML).foreach { c => c.edgesGraphML(buf, pad) } } diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala index 9a4c0497..34d2be29 100644 --- a/src/main/scala/uncore/tilelink2/Nodes.scala +++ b/src/main/scala/uncore/tilelink2/Nodes.scala @@ -15,6 +15,7 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data] def edgeI(pd: DI, pu: UI): EI def bundleI(ei: Seq[EI]): Vec[BI] def mixI(pu: UI, node: InwardNode[DI, UI, BI]): UI = pu + def colour: String def connect(bo: => BI, bi: => BI, e: => EI)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) } @@ -42,11 +43,11 @@ abstract class BaseNode lazyModule.nodes = this :: lazyModule.nodes def name = lazyModule.name + "." + getClass.getName.split('.').last - def colour = "blue" def omitGraphML = outputs.isEmpty && inputs.isEmpty protected[tilelink2] def outputs: Seq[BaseNode] protected[tilelink2] def inputs: Seq[BaseNode] + protected[tilelink2] def colour: String } trait InwardNode[DI, UI, BI <: Data] extends BaseNode @@ -109,6 +110,7 @@ class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( extends BaseNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // meta-data for printing the node graph + protected[tilelink2] def colour = inner.colour protected[tilelink2] def outputs = oPorts.map(_._2) protected[tilelink2] def inputs = iPorts.map(_._2) diff --git a/src/main/scala/uncore/tilelink2/TLNodes.scala b/src/main/scala/uncore/tilelink2/TLNodes.scala index e52b275d..b02c9883 100644 --- a/src/main/scala/uncore/tilelink2/TLNodes.scala +++ b/src/main/scala/uncore/tilelink2/TLNodes.scala @@ -19,6 +19,7 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip } + def colour = "#000000" // black def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { val monitor = LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo)) (Some(monitor), () => { @@ -85,6 +86,7 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor Vec(ei.size, new TLAsyncBundle(ei(0).bundle)).flip } + def colour = "#ff0000" // red def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { (None, () => { bi <> bo }) }