riscv/rocket-chip
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check that MultiWidthFifo count is correct

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This commit is contained in:
Howard Mao
2016-02-17 13:36:07 -08:00
parent 4915a258f6
commit f290157cb3
1 changed files with 8 additions and 0 deletions
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8
groundtest/src/main/scala/unittest.scala
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@@ -75,10 +75,18 @@ class MultiWidthFifoTest extends UnitTest {
io.finished := bl_finished && lb_finished
val bl_start_recv = Reg(next = bl_send_done)
val lb_start_recv = Reg(next = lb_send_done)
assert(!little2big.io.out.valid || little2big.io.out.bits === lb_recv_data,
"Little to Big data mismatch")
assert(!big2little.io.out.valid || big2little.io.out.bits === bl_recv_data,
"Bit to Little data mismatch")
assert(!lb_start_recv || little2big.io.count === UInt(4),
"Little to Big count incorrect")
assert(!bl_start_recv || big2little.io.count === UInt(8),
"Big to Little count incorrect")
}
class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {