From f191bb994cda3e5b5673afa118647385687b12cf Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 11 Aug 2017 18:10:27 -0700 Subject: [PATCH] PatternPusher: can now expect a certain output (#952) --- src/main/scala/tilelink/PatternPusher.scala | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/PatternPusher.scala b/src/main/scala/tilelink/PatternPusher.scala index 1858c925..b384f133 100644 --- a/src/main/scala/tilelink/PatternPusher.scala +++ b/src/main/scala/tilelink/PatternPusher.scala @@ -6,11 +6,13 @@ import Chisel._ import chisel3.internal.sourceinfo.SourceInfo import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.util._ -sealed trait Pattern { +trait Pattern { def address: BigInt def size: Int def bits(edge: TLEdgeOut): (Bool, TLBundleA) + def dataIn: Option[BigInt] = None require ((address & ((BigInt(1) << size) - 1)) == 0) } @@ -25,6 +27,12 @@ case class ReadPattern(address: BigInt, size: Int) extends Pattern def bits(edge: TLEdgeOut) = edge.Get(UInt(0), UInt(address), UInt(size)) } +case class ReadExpectPattern(address: BigInt, size: Int, data: BigInt) extends Pattern +{ + def bits(edge: TLEdgeOut) = edge.Get(UInt(0), UInt(address), UInt(size)) + override def dataIn = Some(data) +} + class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameters) extends LazyModule { val node = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters(name = name))))) @@ -51,6 +59,11 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter val a = io.tl_out(0).a val d = io.tl_out(0).d + // Expected response? + val check = Vec(pattern.map(p => Bool(p.dataIn.isDefined)))(step) holdUnless a.fire() + val expect = Vec(pattern.map(p => UInt(p.dataIn.getOrElse(BigInt(0)))))(step) holdUnless a.fire() + assert (!check || !d.fire() || expect === d.bits.data) + when (a.fire()) { flight := Bool(true) step := step + UInt(1)