working RoCC AccumulatorExample
This commit is contained in:
Andrew Waterman
parent
18968dfbc7
commit
f12bbc1e43
@ -39,6 +39,7 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Modu
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val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UInt(i)
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resp.valid := io.mem.resp.valid && tag_hit
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io.requestor(i).xcpt := io.mem.xcpt
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io.requestor(i).ordered := io.mem.ordered
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resp.bits := io.mem.resp.bits
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resp.bits.tag := io.mem.resp.bits.tag >> UInt(log2Up(n))
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resp.bits.nack := io.mem.resp.bits.nack && tag_hit
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@ -282,25 +282,25 @@ object RoCCDecode extends DecodeConstants
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CUSTOM0-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM0_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM0_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM0-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM0_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM0_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM0_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM1-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM1_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM1_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM1-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM1_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM1_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM1_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM2-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM2_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM2_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM2-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM2_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM2_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM2_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM3-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM3_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM3_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM3-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM3_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM3_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
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CUSTOM3_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N))
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}
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@ -639,7 +639,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
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io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr ||
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io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr ||
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io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr)
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val id_ex_hazard = data_hazard_ex && (ex_reg_pcr != PCR.N || ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val) ||
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val id_ex_hazard = data_hazard_ex && (ex_reg_pcr != PCR.N || ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val || ex_reg_rocc_val) ||
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fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val)
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// stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage.
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@ -655,7 +655,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
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io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr ||
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io.fpu.dec.ren3 && id_raddr3 === io.dpath.mem_waddr ||
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io.fpu.dec.wen && id_waddr === io.dpath.mem_waddr)
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val id_mem_hazard = data_hazard_mem && (mem_reg_pcr != PCR.N || mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val || mem_reg_fp_val) ||
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val id_mem_hazard = data_hazard_mem && (mem_reg_pcr != PCR.N || mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val || mem_reg_fp_val || mem_reg_rocc_val) ||
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fp_data_hazard_mem && mem_reg_fp_val
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id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
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@ -669,7 +669,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
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io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr ||
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io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr ||
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io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr)
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val id_wb_hazard = data_hazard_wb && (wb_dcache_miss || wb_reg_div_mul_val) ||
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val id_wb_hazard = data_hazard_wb && (wb_dcache_miss || wb_reg_div_mul_val || wb_reg_rocc_val) ||
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fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val)
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io.dpath.mem_ll_bypass_rs1 := io.dpath.mem_ll_wb && io.dpath.mem_ll_waddr === id_raddr1
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@ -5,12 +5,13 @@ import Node._
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object DecodeLogic
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{
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def term(b: Literal) = {
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if (b.isZ) {
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var (bits, mask, swidth) = Literal.parseLit(b.toString)
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new Term(BigInt(bits, 2), BigInt(2).pow(b.width)-(BigInt(mask, 2)+1))
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def term(b: Bits) = {
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val lit = b.litOf
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if (lit.isZ) {
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var (bits, mask, swidth) = Literal.parseLit(lit.toString)
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new Term(BigInt(bits, 2), BigInt(2).pow(lit.width)-(BigInt(mask, 2)+1))
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} else {
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new Term(b.value)
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new Term(lit.value)
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}
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}
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def logic(addr: Bits, addrWidth: Int, cache: scala.collection.mutable.Map[Term,Bits], terms: Seq[Term]) = {
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@ -24,18 +25,17 @@ object DecodeLogic
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var map = mapping
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var cache = scala.collection.mutable.Map[Term,Bits]()
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default map { d =>
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val dlit = d.litOf
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val dterm = term(dlit)
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val dterm = term(d)
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val (keys, values) = map.unzip
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val addrWidth = keys.map(_.getWidth).max
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val terms = keys.toList.map(k => term(k.litOf))
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val termvalues = terms zip values.toList.map(v => term(v.head.litOf))
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val terms = keys.toList.map(k => term(k))
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val termvalues = terms zip values.toList.map(v => term(v.head))
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for (t <- terms.tails; if !t.isEmpty)
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for (t <- keys.zip(terms).tails; if !t.isEmpty)
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for (u <- t.tail)
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assert(!t.head.intersects(u), "DecodeLogic: keys " + t + " and " + u + " overlap")
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assert(!t.head._2.intersects(u._2), "DecodeLogic: keys " + t.head + " and " + u + " overlap")
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val result = (0 until math.max(dlit.width, values.map(_.head.litOf.width).max)).map({ case (i: Int) =>
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val result = (0 until math.max(d.litOf.width, values.map(_.head.litOf.width).max)).map({ case (i: Int) =>
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val mint = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 1 }.map(_._1)
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val maxt = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 0 }.map(_._1)
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val dc = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 1 }.map(_._1)
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@ -244,7 +244,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
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val dmem_resp_fpu = io.dmem.resp.bits.tag(0).toBool
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val dmem_resp_waddr = io.dmem.resp.bits.tag.toUInt >> UInt(1)
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val dmem_resp_replay = io.dmem.resp.bits.replay && dmem_resp_xpu
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val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
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val dmem_resp_replay = io.dmem.resp.bits.replay && io.dmem.resp.bits.has_data
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val mem_ll_wdata = Bits()
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mem_ll_wdata := div.io.resp.bits.data
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@ -259,7 +260,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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io.ctrl.mem_ll_wb := Bool(true)
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}
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}
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when (dmem_resp_replay) {
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when (dmem_resp_replay && dmem_resp_xpu) {
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div.io.resp.ready := Bool(false)
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if (!conf.rocc.isEmpty)
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io.rocc.resp.ready := Bool(false)
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@ -269,7 +270,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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}
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when (io.ctrl.mem_ll_waddr === UInt(0)) { io.ctrl.mem_ll_wb := Bool(false) }
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io.fpu.dmem_resp_val := io.dmem.resp.valid && dmem_resp_fpu
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io.fpu.dmem_resp_val := dmem_resp_valid && dmem_resp_fpu
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io.fpu.dmem_resp_data := io.dmem.resp.bits.data
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io.fpu.dmem_resp_type := io.dmem.resp.bits.typ
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io.fpu.dmem_resp_tag := dmem_resp_waddr
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@ -297,7 +298,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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io.ctrl.wb_waddr := wb_reg_waddr
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// scoreboard clear (for div/mul and D$ load miss writebacks)
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io.ctrl.fp_sboard_clr := io.dmem.resp.bits.replay && dmem_resp_fpu
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io.ctrl.fp_sboard_clr := dmem_resp_replay && dmem_resp_fpu
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io.ctrl.fp_sboard_clra := dmem_resp_waddr
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// processor control regfile write
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@ -698,6 +698,7 @@ class HellaCacheResp(implicit val conf: DCacheConfig) extends DCacheBundle {
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val nack = Bool() // comes 2 cycles after req.fire
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val replay = Bool()
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val typ = Bits(width = 3)
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val has_data = Bool()
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val data = Bits(width = conf.databits)
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val data_subword = Bits(width = conf.databits)
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val tag = Bits(width = conf.reqtagbits)
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@ -1027,11 +1028,11 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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io.cpu.req.ready := Bool(false)
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}
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val s2_do_resp = isRead(s2_req.cmd) || s2_sc
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io.cpu.resp.valid := s2_do_resp && (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
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io.cpu.resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
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io.cpu.resp.bits.nack := s2_valid && s2_nack
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io.cpu.resp.bits := s2_req
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io.cpu.resp.bits.replay := s2_replay && s2_do_resp
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io.cpu.resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
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io.cpu.resp.bits.replay := s2_replay
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io.cpu.resp.bits.data := loadgen.word
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io.cpu.resp.bits.data_subword := Mux(s2_sc, s2_sc_fail, loadgen.byte)
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io.cpu.resp.bits.store_data := s2_req.data
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@ -1039,3 +1040,84 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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io.mem.grant_ack <> mshrs.io.mem_finish
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}
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// exposes a sane decoupled request interface
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class SimpleHellaCacheIF(implicit conf: DCacheConfig) extends Module
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{
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val io = new Bundle {
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val requestor = new HellaCacheIO().flip
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val cache = new HellaCacheIO
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}
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val replaying_cmb = Bool()
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val replaying = Reg(next = replaying_cmb, init = Bool(false))
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replaying_cmb := replaying
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val replayq1 = Module(new Queue(new HellaCacheReq, 1, flow = true))
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val replayq2 = Module(new Queue(new HellaCacheReq, 1))
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val req_arb = Module(new Arbiter(new HellaCacheReq, 2))
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req_arb.io.in(0) <> replayq1.io.deq
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req_arb.io.in(1).valid := !replaying_cmb && io.requestor.req.valid
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req_arb.io.in(1).bits := io.requestor.req.bits
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io.requestor.req.ready := !replaying_cmb && req_arb.io.in(1).ready
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val s2_nack = io.cache.resp.bits.nack
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val s3_nack = Reg(next=s2_nack)
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val s0_req_fire = io.cache.req.fire()
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val s1_req_fire = Reg(next=s0_req_fire)
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val s2_req_fire = Reg(next=s1_req_fire)
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io.cache.req.bits.kill := s2_nack
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io.cache.req.bits.phys := Bool(true)
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io.cache.req.bits.data := RegEnable(req_arb.io.out.bits.data, s0_req_fire)
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io.cache.req <> req_arb.io.out
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// replay queues
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// replayq1 holds the older request
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// replayq2 holds the newer request (for the first nack)
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// we need to split the queues like this for the case where the older request
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// goes through but gets nacked, while the newer request stalls
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// if this happens, the newer request will go through before the older
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// request
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// we don't need to check replayq1.io.enq.ready and replayq2.io.enq.ready as
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// there will only be two requests going through at most
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// stash d$ request in stage 2 if nacked (older request)
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replayq1.io.enq.valid := Bool(false)
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replayq1.io.enq.bits.cmd := io.cache.resp.bits.cmd
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replayq1.io.enq.bits.typ := io.cache.resp.bits.typ
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replayq1.io.enq.bits.addr := io.cache.resp.bits.addr
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replayq1.io.enq.bits.data := io.cache.resp.bits.store_data
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replayq1.io.enq.bits.tag := io.cache.resp.bits.tag
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// stash d$ request in stage 1 if nacked (newer request)
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replayq2.io.enq.valid := s2_req_fire && s3_nack
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replayq2.io.enq.bits.data := io.cache.resp.bits.store_data
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replayq2.io.enq.bits <> io.cache.resp.bits
|
||||
replayq2.io.deq.ready := Bool(false)
|
||||
|
||||
when (s2_nack) {
|
||||
replayq1.io.enq.valid := Bool(true)
|
||||
replaying_cmb := Bool(true)
|
||||
}
|
||||
|
||||
// when replaying request got sunk into the d$
|
||||
when (s2_req_fire && Reg(next=Reg(next=replaying_cmb)) && !s2_nack) {
|
||||
// see if there's a stashed request in replayq2
|
||||
when (replayq2.io.deq.valid) {
|
||||
replayq1.io.enq.valid := Bool(true)
|
||||
replayq1.io.enq.bits.cmd := replayq2.io.deq.bits.cmd
|
||||
replayq1.io.enq.bits.typ := replayq2.io.deq.bits.typ
|
||||
replayq1.io.enq.bits.addr := replayq2.io.deq.bits.addr
|
||||
replayq1.io.enq.bits.data := replayq2.io.deq.bits.data
|
||||
replayq1.io.enq.bits.tag := replayq2.io.deq.bits.tag
|
||||
replayq2.io.deq.ready := Bool(true)
|
||||
} .otherwise {
|
||||
replaying_cmb := Bool(false)
|
||||
}
|
||||
}
|
||||
|
||||
io.requestor.resp := io.cache.resp
|
||||
}
|
||||
|
||||
@ -2,6 +2,7 @@ package rocket
|
||||
|
||||
import Chisel._
|
||||
import Node._
|
||||
import uncore._
|
||||
|
||||
class RoCCInstruction extends Bundle
|
||||
{
|
||||
@ -36,35 +37,73 @@ class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
|
||||
{
|
||||
val cmd = Decoupled(new RoCCCommand).flip
|
||||
val resp = Decoupled(new RoCCResponse)
|
||||
val mem = new HellaCacheIO()(conf.dcache)
|
||||
val busy = Bool(OUTPUT)
|
||||
val interrupt = Bool(OUTPUT)
|
||||
|
||||
override def clone = new RoCCInterface().asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
abstract class RoCC(implicit conf: RocketConfiguration) extends Module
|
||||
abstract class RoCC(conf: RocketConfiguration) extends Module
|
||||
{
|
||||
val io = new RoCCInterface
|
||||
val io = new RoCCInterface()(conf)
|
||||
}
|
||||
|
||||
class AccumulatorExample(implicit conf: RocketConfiguration) extends RoCC
|
||||
class AccumulatorExample(conf: RocketConfiguration) extends RoCC(conf)
|
||||
{
|
||||
val regfile = Mem(UInt(width = conf.xprlen), 4)
|
||||
val n = 4
|
||||
val regfile = Mem(UInt(width = conf.xprlen), n)
|
||||
val busy = Vec.fill(n){Reg(init=Bool(false))}
|
||||
|
||||
val funct = io.cmd.bits.inst.funct
|
||||
val addr = io.cmd.bits.inst.rs2
|
||||
val addend = io.cmd.bits.rs1
|
||||
val cmd = Queue(io.cmd)
|
||||
val funct = cmd.bits.inst.funct
|
||||
val addr = cmd.bits.inst.rs2(log2Up(n)-1,0)
|
||||
val doWrite = funct === UInt(0)
|
||||
val doRead = funct === UInt(1)
|
||||
val doLoad = funct === UInt(2)
|
||||
val doAccum = funct === UInt(3)
|
||||
val memRespTag = io.mem.resp.bits.tag(log2Up(n)-1,0)
|
||||
|
||||
// datapath
|
||||
val addend = cmd.bits.rs1
|
||||
val accum = regfile(addr)
|
||||
val wdata = Mux(funct === UInt(0), addend, accum + addend)
|
||||
val wdata = Mux(doWrite, addend, accum + addend)
|
||||
|
||||
when (io.cmd.fire() && (funct === UInt(1) || funct === UInt(3))) {
|
||||
when (cmd.fire() && (doWrite || doAccum)) {
|
||||
regfile(addr) := wdata
|
||||
}
|
||||
|
||||
io.cmd.ready := io.resp.ready
|
||||
io.resp.valid := io.cmd.valid && io.cmd.bits.inst.xd
|
||||
io.resp.bits.rd := io.cmd.bits.inst.rd
|
||||
when (io.mem.resp.valid) {
|
||||
regfile(memRespTag) := io.mem.resp.bits.data
|
||||
}
|
||||
|
||||
// control
|
||||
when (io.mem.req.fire()) {
|
||||
busy(addr) := Bool(true)
|
||||
}
|
||||
|
||||
when (io.mem.resp.valid) {
|
||||
busy(memRespTag) := Bool(false)
|
||||
}
|
||||
|
||||
val doResp = cmd.bits.inst.xd
|
||||
val stallReg = busy(addr)
|
||||
val stallLoad = doLoad && !io.mem.req.ready
|
||||
val stallResp = doResp && !io.resp.ready
|
||||
|
||||
cmd.ready := !stallReg && !stallLoad && !stallResp
|
||||
|
||||
io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad
|
||||
io.resp.bits.rd := cmd.bits.inst.rd
|
||||
io.resp.bits.data := accum
|
||||
|
||||
io.busy := Bool(false)
|
||||
io.interrupt := Bool(false)
|
||||
|
||||
io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
|
||||
io.mem.req.bits.addr := addend
|
||||
io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
|
||||
io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
|
||||
io.mem.req.bits.data := Bits(0) // we're not performing any stores...
|
||||
io.mem.req.bits.phys := Bool(true) // don't perform address translation
|
||||
}
|
||||
|
||||
@ -6,7 +6,7 @@ import Util._
|
||||
|
||||
case class RocketConfiguration(tl: TileLinkConfiguration,
|
||||
icache: ICacheConfig, dcache: DCacheConfig,
|
||||
fpu: Boolean, rocc: Option[RoCC] = None,
|
||||
fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None,
|
||||
fastLoadWord: Boolean = true,
|
||||
fastLoadByte: Boolean = false,
|
||||
fastMulDiv: Boolean = true)
|
||||
@ -23,7 +23,6 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
|
||||
val memPorts = 2
|
||||
val dcachePortId = 0
|
||||
val icachePortId = 1
|
||||
val vicachePortId = 2
|
||||
implicit val tlConf = confIn.tl
|
||||
implicit val lnConf = confIn.tl.ln
|
||||
implicit val icConf = confIn.icache
|
||||
@ -48,6 +47,18 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
|
||||
ptw.io.requestor(0) <> icache.io.cpu.ptw
|
||||
ptw.io.requestor(1) <> dcache.io.cpu.ptw
|
||||
|
||||
if (!conf.rocc.isEmpty) {
|
||||
val dcIF = Module(new SimpleHellaCacheIF)
|
||||
val rocc = Module((conf.rocc.get)(conf))
|
||||
dcIF.io.requestor <> rocc.io.mem
|
||||
core.io.rocc <> rocc.io
|
||||
dcacheArb.io.requestor(2) <> dcIF.io.cache
|
||||
}
|
||||
|
||||
core.io.host <> io.host
|
||||
core.io.imem <> icache.io.cpu
|
||||
core.io.ptw <> ptw.io.dpath
|
||||
|
||||
val memArb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(memPorts))
|
||||
memArb.io.in(dcachePortId) <> dcache.io.mem
|
||||
memArb.io.in(icachePortId) <> icache.io.mem
|
||||
@ -61,8 +72,4 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
|
||||
dcache.io.mem.release.meta.ready := io.tilelink.release.meta.ready
|
||||
io.tilelink.release.meta.bits := dcache.io.mem.release.meta.bits
|
||||
io.tilelink.release.meta.bits.payload.client_xact_id := Cat(dcache.io.mem.release.meta.bits.payload.client_xact_id, UInt(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
|
||||
|
||||
core.io.host <> io.host
|
||||
core.io.imem <> icache.io.cpu
|
||||
core.io.ptw <> ptw.io.dpath
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user