riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

axi4: RegisterRouter; concurrent response illegal in AXI

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-04-21 16:59:59 -07:00
parent 5163ccd11f
commit f1217519f1
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/uncore/axi4/RegisterRouter.scala
View File

@ -17,7 +17,7 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
supportsRead = TransferSizes(1, beatBytes), supportsRead = TransferSizes(1, beatBytes),
interleavedId = Some(0))), interleavedId = Some(0))),
beatBytes = beatBytes, beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) // the Queue adds at most one cycle minLatency = 1)))
{ {
require (address.contiguous) require (address.contiguous)
@ -54,7 +54,7 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
// Invoke the register map builder and make it Irrevocable // Invoke the register map builder and make it Irrevocable
val out = Queue.irrevocable( val out = Queue.irrevocable(
RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*), RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
entries = 1, flow = true) entries = 2)
// No flow control needed // No flow control needed
out.ready := Mux(out.bits.read, r.ready, b.ready) out.ready := Mux(out.bits.read, r.ready, b.ready)