riscv/rocket-chip
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Pass correct access size information to PMP checker

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This commit is contained in:
Andrew Waterman
2017-03-15 15:18:56 -07:00
parent a6874c03f7
commit f0796f0509
4 changed files with 15 additions and 9 deletions
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3
src/main/scala/rocket/NBDcache.scala
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@ -697,7 +697,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
val s1_write = isWrite(s1_req.cmd)
val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
val dtlb = Module(new TLB(nTLBEntries))
val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> dtlb.io.ptw
dtlb.io.req.valid := s1_valid_masked && (s1_readwrite || s1_sfence)
dtlb.io.req.bits.sfence.valid := s1_sfence
@ -708,6 +708,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
dtlb.io.req.bits.vaddr := s1_req.addr
dtlb.io.req.bits.instruction := Bool(false)
dtlb.io.req.bits.store := s1_write
dtlb.io.req.bits.size := s1_req.typ
when (!dtlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := Bool(false) }
when (io.cpu.req.valid) {