tilelink2: move general-purpose code out of tilelink2 package
This commit is contained in:
Wesley W. Terpstra
@ -3,147 +3,9 @@
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package uncore.tilelink2
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import Chisel._
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import diplomacy._
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import scala.math.max
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/** Options for memory regions */
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object RegionType {
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sealed trait T
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case object CACHED extends T
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case object TRACKED extends T
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case object UNCACHED extends T
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case object PUT_EFFECTS extends T
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case object GET_EFFECTS extends T // GET_EFFECTS => PUT_EFFECTS
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val cases = Seq(CACHED, TRACKED, UNCACHED, PUT_EFFECTS, GET_EFFECTS)
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}
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// A non-empty half-open range; [start, end)
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case class IdRange(start: Int, end: Int)
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{
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require (start >= 0)
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require (start < end) // not empty
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// This is a strict partial ordering
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def <(x: IdRange) = end <= x.start
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def >(x: IdRange) = x < this
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def overlaps(x: IdRange) = start < x.end && x.start < end
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def contains(x: IdRange) = start <= x.start && x.end <= end
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// contains => overlaps (because empty is forbidden)
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def contains(x: Int) = start <= x && x < end
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def contains(x: UInt) =
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if (start+1 == end) { UInt(start) === x }
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else if (isPow2(end-start) && ((end | start) & (end-start-1)) == 0)
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{ ~(~(UInt(start) ^ x) | UInt(end-start-1)) === UInt(0) }
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else { UInt(start) <= x && x < UInt(end) }
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def shift(x: Int) = IdRange(start+x, end+x)
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def size = end - start
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}
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// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
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case class TransferSizes(min: Int, max: Int)
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{
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def this(x: Int) = this(x, x)
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require (min <= max)
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require (min >= 0 && max >= 0)
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require (max == 0 || isPow2(max))
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require (min == 0 || isPow2(min))
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require (max == 0 || min != 0) // 0 is forbidden unless (0,0)
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def none = min == 0
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def contains(x: Int) = isPow2(x) && min <= x && x <= max
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def containsLg(x: Int) = contains(1 << x)
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def containsLg(x: UInt) =
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if (none) Bool(false)
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else if (min == max) { UInt(log2Ceil(min)) === x }
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else { UInt(log2Ceil(min)) <= x && x <= UInt(log2Ceil(max)) }
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def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
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def intersect(x: TransferSizes) =
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if (x.max < min || max < x.min) TransferSizes.none
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else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
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}
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object TransferSizes {
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def apply(x: Int) = new TransferSizes(x)
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val none = new TransferSizes(0)
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implicit def asBool(x: TransferSizes) = !x.none
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}
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// AddressSets specify the address space managed by the manager
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// Base is the base address, and mask are the bits consumed by the manager
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// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
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// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
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case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
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{
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// Forbid misaligned base address (and empty sets)
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require ((base & mask) == 0)
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require (base >= 0) // TL2 address widths are not fixed => negative is ambiguous
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// We do allow negative mask (=> ignore all high bits)
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def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
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def contains(x: UInt) = ((x ^ UInt(base)).zext() & SInt(~mask)) === SInt(0)
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// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
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def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
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// contains iff bitwise: x.mask => mask && contains(x.base)
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def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
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// The number of bytes to which the manager must be aligned
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def alignment = ((mask + 1) & ~mask)
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// Is this a contiguous memory range
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def contiguous = alignment == mask+1
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def finite = mask >= 0
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def max = { require (finite); base | mask }
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// Widen the match function to ignore all bits in imask
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def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
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// AddressSets have one natural Ordering (the containment order, if contiguous)
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def compare(x: AddressSet) = {
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val primary = (this.base - x.base).signum // smallest address first
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val secondary = (x.mask - this.mask).signum // largest mask first
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if (primary != 0) primary else secondary
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}
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// We always want to see things in hex
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override def toString() = {
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if (mask >= 0) {
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"AddressSet(0x%x, 0x%x)".format(base, mask)
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} else {
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"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
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}
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}
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}
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object AddressSet
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{
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def misaligned(base: BigInt, size: BigInt): Seq[AddressSet] = {
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val largestPow2 = BigInt(1) << log2Floor(size)
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val mostZeros = (base + size - 1) & ~(largestPow2 - 1)
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def splitLo(low: BigInt, high: BigInt, tail: Seq[AddressSet]): Seq[AddressSet] = {
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if (low == high) tail else {
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val toggleBits = low ^ high
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val misalignment = toggleBits & (-toggleBits)
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splitLo(low+misalignment, high, AddressSet(low, misalignment-1) +: tail)
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}
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}
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def splitHi(low: BigInt, high: BigInt, tail: Seq[AddressSet]): Seq[AddressSet] = {
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if (low == high) tail else {
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val toggleBits = low ^ high
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val misalignment = toggleBits & (-toggleBits)
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splitHi(low, high-misalignment, AddressSet(high-misalignment, misalignment-1) +: tail)
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}
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}
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splitLo(base, mostZeros, splitHi(mostZeros, base+size, Seq())).sorted
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}
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}
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case class TLManagerParameters(
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address: Seq[AddressSet],
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sinkId: IdRange = IdRange(0, 1),
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