tilelink2: move general-purpose code out of tilelink2 package
This commit is contained in:
Wesley W. Terpstra
@ -3,191 +3,124 @@
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package uncore.tilelink2
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import Chisel._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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import diplomacy._
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import scala.collection.mutable.ListBuffer
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// DI = Downwards flowing Parameters received on the inner side of the node
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// UI = Upwards flowing Parameters generated by the inner side of the node
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// EI = Edge Parameters describing a connection on the inner side of the node
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// BI = Bundle type used when connecting to the inner side of the node
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trait InwardNodeImp[DI, UI, EI, BI <: Data]
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeI(pd: DI, pu: UI): EI
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def bundleI(ei: Seq[EI]): Vec[BI]
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def mixI(pu: UI, node: InwardNode[DI, UI, BI]): UI = pu
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def colour: String
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def connect(bo: => BI, bi: => BI, e: => EI)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit)
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}
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// DO = Downwards flowing Parameters generated by the outner side of the node
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// UO = Upwards flowing Parameters received on the outner side of the node
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// EO = Edge Parameters describing a connection on the outer side of the node
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// BO = Bundle type used when connecting to the outer side of the node
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trait OutwardNodeImp[DO, UO, EO, BO <: Data]
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{
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def edgeO(pd: DO, pu: UO): EO
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def bundleO(eo: Seq[EO]): Vec[BO]
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def mixO(pd: DO, node: OutwardNode[DO, UO, BO]): DO = pd
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}
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abstract class NodeImp[D, U, EO, EI, B <: Data]
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extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B]
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abstract class BaseNode
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{
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// You cannot create a Node outside a LazyModule!
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require (!LazyModule.stack.isEmpty)
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val lazyModule = LazyModule.stack.head
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val index = lazyModule.nodes.size
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lazyModule.nodes = this :: lazyModule.nodes
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def name = lazyModule.name + "." + getClass.getName.split('.').last
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def omitGraphML = outputs.isEmpty && inputs.isEmpty
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protected[tilelink2] def outputs: Seq[BaseNode]
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protected[tilelink2] def inputs: Seq[BaseNode]
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protected[tilelink2] def colour: String
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}
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trait InwardNode[DI, UI, BI <: Data] extends BaseNode
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{
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protected[tilelink2] val numPI: Range.Inclusive
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require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
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require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
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private val accPI = ListBuffer[(Int, OutwardNode[DI, UI, BI])]()
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private var iRealized = false
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protected[tilelink2] def iPushed = accPI.size
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protected[tilelink2] def iPush(index: Int, node: OutwardNode[DI, UI, BI])(implicit sourceInfo: SourceInfo) {
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val info = sourceLine(sourceInfo, " at ", "")
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val noIs = numPI.size == 1 && numPI.contains(0)
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require (!noIs, s"${name}${lazyModule.line} was incorrectly connected as a sink" + info)
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require (!iRealized, s"${name}${lazyModule.line} was incorrectly connected as a sink after it's .module was used" + info)
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accPI += ((index, node))
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def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
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def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(pd, pu)
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def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
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require (!eo.isEmpty)
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Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
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}
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def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = {
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require (!ei.isEmpty)
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Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
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}
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private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}")
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protected[tilelink2] lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
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protected[tilelink2] val iParams: Seq[UI]
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protected[tilelink2] def iConnect: Vec[BI]
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}
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trait OutwardNode[DO, UO, BO <: Data] extends BaseNode
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{
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protected[tilelink2] val numPO: Range.Inclusive
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require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
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require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
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private val accPO = ListBuffer[(Int, InwardNode [DO, UO, BO])]()
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private var oRealized = false
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protected[tilelink2] def oPushed = accPO.size
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protected[tilelink2] def oPush(index: Int, node: InwardNode [DO, UO, BO])(implicit sourceInfo: SourceInfo) {
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val info = sourceLine(sourceInfo, " at ", "")
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val noOs = numPO.size == 1 && numPO.contains(0)
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require (!noOs, s"${name}${lazyModule.line} was incorrectly connected as a source" + info)
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require (!oRealized, s"${name}${lazyModule.line} was incorrectly connected as a source after it's .module was used" + info)
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accPO += ((index, node))
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def colour = "#000000" // black
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def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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val monitor = LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo))
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(Some(monitor), () => {
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bi <> bo
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monitor.module.io.in := TLBundleSnoop(bo)
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})
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}
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private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
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protected[tilelink2] lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
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protected[tilelink2] val oParams: Seq[DO]
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protected[tilelink2] def oConnect: Vec[BO]
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override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLClientPortParameters =
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pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) })
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override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLManagerPortParameters =
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pu.copy(managers = pu.managers.map { m => m.copy (nodePath = node +: m.nodePath) })
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}
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class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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private val dFn: (Int, Seq[DI]) => Seq[DO],
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private val uFn: (Int, Seq[UO]) => Seq[UI],
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protected[tilelink2] val numPO: Range.Inclusive,
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protected[tilelink2] val numPI: Range.Inclusive)
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extends BaseNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
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{
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// meta-data for printing the node graph
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protected[tilelink2] def colour = inner.colour
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protected[tilelink2] def outputs = oPorts.map(_._2)
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protected[tilelink2] def inputs = iPorts.map(_._2)
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case class TLIdentityNode() extends IdentityNode(TLImp)
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case class TLOutputNode() extends OutputNode(TLImp)
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case class TLInputNode() extends InputNode(TLImp)
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private def reqE(o: Int, i: Int) = require(i == o, s"${name} has ${i} inputs and ${o} outputs; they must match${lazyModule.line}")
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protected[tilelink2] lazy val oParams: Seq[DO] = {
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val o = dFn(oPorts.size, iPorts.map { case (i, n) => n.oParams(i) })
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reqE(oPorts.size, o.size)
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o.map(outer.mixO(_, this))
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}
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protected[tilelink2] lazy val iParams: Seq[UI] = {
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val i = uFn(iPorts.size, oPorts.map { case (o, n) => n.iParams(o) })
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reqE(i.size, iPorts.size)
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i.map(inner.mixI(_, this))
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case class TLClientNode(portParams: TLClientPortParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SourceNode(TLImp)(portParams, numPorts)
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case class TLManagerNode(portParams: TLManagerPortParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SinkNode(TLImp)(portParams, numPorts)
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object TLClientNode
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{
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def apply(params: TLClientParameters) =
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new TLClientNode(TLClientPortParameters(Seq(params)), 1 to 1)
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}
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object TLManagerNode
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{
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def apply(beatBytes: Int, params: TLManagerParameters) =
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new TLManagerNode(TLManagerPortParameters(Seq(params), beatBytes, 0), 1 to 1)
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}
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case class TLAdapterNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
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/** Synthesizeable unit tests */
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import unittest._
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class TLInputNodeTest extends UnitTest(500000) {
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class Acceptor extends LazyModule {
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val node = TLInputNode()
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val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
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tlram.node := node
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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}
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}
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lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => outer.edgeO(o, n.iParams(i)) }
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lazy val edgesIn = (iPorts zip iParams).map { case ((o, n), i) => inner.edgeI(n.oParams(o), i) }
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val fuzzer = LazyModule(new TLFuzzer(5000))
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LazyModule(new Acceptor).node := TLFragmenter(4, 64)(fuzzer.node)
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lazy val bundleOut = outer.bundleO(edgesOut)
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lazy val bundleIn = inner.bundleI(edgesIn)
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io.finished := Module(fuzzer.module).io.finished
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}
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def oConnect = bundleOut
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def iConnect = bundleIn
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// connects the outward part of a node with the inward part of this node
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def := (y: OutwardNode[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = {
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val x = this // x := y
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val info = sourceLine(sourceInfo, " at ", "")
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require (!LazyModule.stack.isEmpty, s"${y.name} cannot be connected to ${x.name} outside of LazyModule scope" + info)
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val i = x.iPushed
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val o = y.oPushed
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y.oPush(i, x)
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x.iPush(o, y)
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val (out, binding) = inner.connect(y.oConnect(o), x.iConnect(i), x.edgesIn(i))
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LazyModule.stack.head.bindings = binding :: LazyModule.stack.head.bindings
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out
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object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncEdgeParameters, TLAsyncBundle]
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{
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def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
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def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
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def bundleO(eo: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = {
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require (eo.size == 1)
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Vec(eo.size, new TLAsyncBundle(eo(0).bundle))
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}
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def bundleI(ei: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = {
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require (ei.size == 1)
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Vec(ei.size, new TLAsyncBundle(ei(0).bundle)).flip
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}
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def colour = "#ff0000" // red
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def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => { bi <> bo })
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}
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override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
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pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) }))
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override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
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pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
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}
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class SimpleNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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oFn: (Int, Seq[D]) => Seq[D],
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iFn: (Int, Seq[U]) => Seq[U],
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numPO: Range.Inclusive,
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numPI: Range.Inclusive)
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extends MixedNode[D, U, EI, B, D, U, EO, B](imp, imp)(oFn, iFn, numPO, numPI)
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case class TLAsyncIdentityNode() extends IdentityNode(TLAsyncImp)
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case class TLAsyncOutputNode() extends OutputNode(TLAsyncImp)
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case class TLAsyncInputNode() extends InputNode(TLAsyncImp)
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class IdentityNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
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extends SimpleNode(imp)({case (_, s) => s}, {case (_, s) => s}, 0 to 999, 0 to 999)
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case class TLAsyncSourceNode() extends MixedNode(TLImp, TLAsyncImp)(
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dFn = { case (1, s) => s.map(TLAsyncClientPortParameters(_)) },
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uFn = { case (1, s) => s.map(_.base) },
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numPO = 1 to 1,
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numPI = 1 to 1)
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class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
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{
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override def oConnect = bundleOut
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override def iConnect = bundleOut
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}
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class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
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{
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override def oConnect = bundleIn
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override def iConnect = bundleIn
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}
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class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
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extends SimpleNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, num, 0 to 0)
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{
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require (num.end >= 1, s"${name} is a source which does not accept outputs${lazyModule.line}")
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}
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class SinkNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
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extends SimpleNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, num)
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{
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require (num.end >= 1, s"${name} is a sink which does not accept inputs${lazyModule.line}")
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}
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class InteriorNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
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(oFn: Seq[PO] => PO, iFn: Seq[PI] => PI, numPO: Range.Inclusive, numPI: Range.Inclusive)
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extends SimpleNode(imp)({case (n,s) => Seq.fill(n)(oFn(s))}, {case (n,s) => Seq.fill(n)(iFn(s))}, numPO, numPI)
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{
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require (numPO.end >= 1, s"${name} is an adapter which does not accept outputs${lazyModule.line}")
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require (numPI.end >= 1, s"${name} is an adapter which does not accept inputs${lazyModule.line}")
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}
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case class TLAsyncSinkNode(depth: Int) extends MixedNode(TLAsyncImp, TLImp)(
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dFn = { case (1, s) => s.map(_.base) },
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uFn = { case (1, s) => s.map(TLAsyncManagerPortParameters(depth, _)) },
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numPO = 1 to 1,
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numPI = 1 to 1)
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