riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

testconfigs: disable atomics until AtomicAbsorber finished

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-09-15 21:15:30 -07:00
parent 38a9421c75
commit f05222a072
2 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/tilelink2/Legacy.scala
View File

@ -78,6 +78,8 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
MemoryOpConstants.M_XA_MINU -> edge.Arithmetic(source, address, beat, data, TLAtomics.MINU)._2,
MemoryOpConstants.M_XA_MAXU -> edge.Arithmetic(source, address, beat, data, TLAtomics.MAXU)._2))
} else {
// If no managers support atomics, assert fail if TL1 asks for them
assert (!io.legacy.acquire.valid || io.legacy.acquire.bits.a_type =/= Acquire.putAtomicType)
Wire(new TLBundleA(edge.bundle))
}