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tile: BaseTile refactor, pt 2

* 2 layer cake
* no more bundle traits, only call to IO
This commit is contained in:
Henry Cook 2018-01-02 15:37:31 -08:00
parent 1579ddb97e
commit efe7165b54
12 changed files with 49 additions and 93 deletions

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@ -32,7 +32,7 @@ trait HasTilesModuleImp extends LazyModuleImp
def resetVectorBits: Int = {
// Consider using the minimum over all widths, rather than enforcing homogeneity
val vectors = outer.tiles.map(_.module.io.reset_vector)
val vectors = outer.tiles.map(_.module.constants.reset_vector)
require(vectors.tail.forall(_.getWidth == vectors.head.getWidth))
vectors.head.getWidth
}
@ -45,8 +45,8 @@ trait HasTilesModuleImp extends LazyModuleImp
outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) =>
tile.clock := wire.clock
tile.reset := wire.reset
tile.io.hartid := wire.hartid
tile.io.reset_vector := wire.reset_vector
tile.constants.hartid := wire.hartid
tile.constants.reset_vector := wire.reset_vector
}
}

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@ -44,9 +44,9 @@ class GroundTestCoreplexModule[+L <: GroundTestCoreplex](_outer: L) extends Base
with HasMasterAXI4MemPortModuleImp {
val success = IO(Bool(OUTPUT))
outer.tiles.zipWithIndex.map { case(t, i) => t.module.io.hartid := UInt(i) }
outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := UInt(i) }
val status = DebugCombiner(outer.tiles.map(_.module.io.status))
val status = DebugCombiner(outer.tiles.map(_.module.status))
success := status.finished
}

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@ -39,15 +39,12 @@ abstract class GroundTestTile(params: GroundTestTileParams)
val dcacheOpt = params.dcache.map { dc => LazyModule(new DCache(0)) }
override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this))
override lazy val module = new GroundTestTileModule(this)
}
class GroundTestTileBundle[+L <: GroundTestTile](_outer: L) extends BaseTileBundle(_outer) {
val status = new GroundTestStatus
class GroundTestTileModule(outer: GroundTestTile) extends BaseTileModule(outer) {
val status = IO(new GroundTestStatus)
val halt_and_catch_fire = None
}
class GroundTestTileModule[+L <: GroundTestTile, +B <: GroundTestTileBundle[L]](_outer: L, _io: () => B) extends BaseTileModule(_outer, _io) {
outer.dcacheOpt foreach { dcache =>
val ptw = Module(new DummyPTW(1))

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@ -583,10 +583,10 @@ class TraceGenTile(val id: Int, val params: TraceGenParams)(implicit p: Paramete
override lazy val module = new TraceGenTileModule(this)
}
class TraceGenTileModule(outer: TraceGenTile) extends GroundTestTileModule(outer, () => new GroundTestTileBundle(outer)) {
class TraceGenTileModule(outer: TraceGenTile) extends GroundTestTileModule(outer) {
val tracegen = Module(new TraceGenerator(outer.params))
tracegen.io.hartid := io.hartid
tracegen.io.hartid := constants.hartid
outer.dcacheOpt foreach { dcache =>
val dcacheIF = Module(new SimpleHellaCacheIF())
@ -594,10 +594,10 @@ class TraceGenTileModule(outer: TraceGenTile) extends GroundTestTileModule(outer
dcache.module.io.cpu <> dcacheIF.io.cache
}
io.status.finished := tracegen.io.finished
io.status.timeout.valid := tracegen.io.timeout
io.status.timeout.bits := UInt(0)
io.status.error.valid := Bool(false)
status.finished := tracegen.io.finished
status.timeout.valid := tracegen.io.timeout
status.timeout.bits := UInt(0)
status.error.valid := Bool(false)
assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out")
}

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@ -315,10 +315,6 @@ trait HasICacheFrontend extends CanHavePTW { this: BaseTile =>
nPTWPorts += 1
}
trait HasICacheFrontendBundle {
val outer: HasICacheFrontend
}
trait HasICacheFrontendModule extends CanHavePTWModule {
val outer: HasICacheFrontend
ptwPorts += outer.frontend.module.io.ptw

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@ -194,7 +194,7 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
/** Mix-ins for constructing tiles that have a HellaCache */
trait HasHellaCache extends HasTileParameters { this: BaseTile =>
trait HasHellaCache { this: BaseTile =>
val module: HasHellaCacheModule
implicit val p: Parameters
def findScratchpadFromICache: Option[AddressSet]
@ -207,13 +207,8 @@ trait HasHellaCache extends HasTileParameters { this: BaseTile =>
tlMasterXbar.node := dcache.node
}
trait HasHellaCacheBundle {
val outer: HasHellaCache
}
trait HasHellaCacheModule {
val outer: HasHellaCache
//val io: HasHellaCacheBundle
val dcachePorts = ListBuffer[HellaCacheIO]()
val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p))
outer.dcache.module.io.cpu <> dcacheArb.io.mem

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@ -287,8 +287,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
}
/** Mix-ins for constructing tiles that might have a PTW */
trait CanHavePTW extends HasHellaCache { this: BaseTile =>
implicit val p: Parameters
trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile =>
val module: CanHavePTWModule
var nPTWPorts = 1
nDCachePorts += usingPTW.toInt

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@ -137,10 +137,6 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend { this: Bas
nDCachePorts += (scratch.isDefined).toInt
}
trait CanHaveScratchpadBundle extends HasHellaCacheBundle with HasICacheFrontendBundle {
val outer: CanHaveScratchpad
}
trait CanHaveScratchpadModule extends HasHellaCacheModule with HasICacheFrontendModule {
val outer: CanHaveScratchpad

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@ -121,35 +121,11 @@ trait HasTileParameters {
}
abstract class BareTile(implicit p: Parameters) extends LazyModule
abstract class BareTileBundle[+L <: BareTile](_outer: L) extends GenericParameterizedBundle(_outer) {
val outer = _outer
implicit val p = outer.p
}
abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
val outer = _outer
val io = IO(_io ())
}
/** Some other standard inputs */
trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
val hartid = UInt(INPUT, hartIdLen)
val reset_vector = UInt(INPUT, resetVectorLen)
}
trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
val trace = tileParams.trace.option(Vec(tileParams.core.retireWidth, new TracedInstruction).asOutput)
}
/** Base class for all Tiles that use TileLink */
abstract class BaseTile(
tileParams: TileParams,
val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends BareTile
with HasTileParameters
with HasCrossing {
def module: BaseTileModule[BaseTile, BaseTileBundle[BaseTile]]
abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCrossing)
(implicit p: Parameters) extends LazyModule with HasTileParameters with HasCrossing
{
def module: BaseTileModule[BaseTile]
def masterNode: TLOutwardNode
def slaveNode: TLInwardNode
def intInwardNode: IntInwardNode
@ -195,16 +171,22 @@ abstract class BaseTile(
}
}
abstract class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
with HasExternallyDrivenTileConstants
with CanHaveInstructionTracePort
with CanHaltAndCatchFire
class BaseTileModule[+L <: BaseTile](val outer: L) extends LazyModuleImp(outer) with HasTileParameters {
class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
with HasTileParameters {
require(xLen == 32 || xLen == 64)
require(paddrBits <= maxPAddrBits)
require(resetVectorLen <= xLen)
require(resetVectorLen <= vaddrBitsExtended)
require (log2Up(hartId + 1) <= hartIdLen, s"p(MaxHartIdBits) of $hartIdLen is not enough for hartid $hartId")
val trace = tileParams.trace.option(IO(Vec(tileParams.core.retireWidth, new TracedInstruction).asOutput))
val constants = IO(new TileInputConstants)
}
/** Some other non-tilelink but still standard inputs */
trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
val hartid = UInt(INPUT, hartIdLen)
val reset_vector = UInt(INPUT, resetVectorLen)
}
class TileInputConstants(implicit val p: Parameters) extends ParameterizedBundle with HasExternallyDrivenTileConstants

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@ -875,11 +875,8 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
}
}
/** Mix-ins for constructing tiles that may have an FPU external to the core pipeline */
trait CanHaveSharedFPU extends HasTileParameters
trait CanHaveSharedFPUModule {
val outer: CanHaveSharedFPU
/** Mix-in for constructing tiles that may have an FPU external to the core pipeline */
trait CanHaveSharedFPUModule[+L <: BaseTile] { this: BaseTileModule[L] =>
val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
// TODO fpArb could go here instead of inside LegacyRoccComplex
}

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@ -77,10 +77,7 @@ class LazyRoCCModule(outer: LazyRoCC) extends LazyModuleImp(outer) {
/** Mixins for including RoCC **/
trait HasLazyRoCC extends CanHaveSharedFPU with CanHavePTW { this: BaseTile =>
implicit val p: Parameters
val module: HasLazyRoCCModule
trait HasLazyRoCC extends CanHavePTW { this: BaseTile =>
val roccs = p(BuildRoCC).zipWithIndex.map { case (accelParams, i) =>
accelParams.generator(p.alterPartial({
case RoccNPTWPorts => accelParams.nPTWPorts
@ -93,10 +90,10 @@ trait HasLazyRoCC extends CanHaveSharedFPU with CanHavePTW { this: BaseTile =>
nDCachePorts += roccs.size
}
trait HasLazyRoCCModule extends CanHaveSharedFPUModule
with CanHavePTWModule
with HasCoreParameters {
val outer: HasLazyRoCC
trait HasLazyRoCCModule[+L <: BaseTile with HasLazyRoCC] extends CanHaveSharedFPUModule[L]
with CanHavePTWModule
with HasCoreParameters { this: BaseTileModule[L] =>
val roccCore = Wire(new RoCCCoreIO()(outer.p))
val buildRocc = outer.p(BuildRoCC)

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@ -56,27 +56,24 @@ class RocketTile(
override lazy val module = new RocketTileModule(this)
}
class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
with CanHaltAndCatchFire {
val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(Bool(OUTPUT))
}
class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
with HasLazyRoCCModule
class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer)
with HasLazyRoCCModule[RocketTile]
with CanHaveScratchpadModule {
val core = Module(p(BuildCore)(outer.p))
val uncorrectable = RegInit(Bool(false))
val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(IO(Bool(OUTPUT)))
outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
outer.busErrorUnit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt }
core.io.hartid := io.hartid // Pass through the hartid
io.trace.foreach { _ := core.io.trace }
io.halt_and_catch_fire.foreach { _ := uncorrectable }
core.io.hartid := constants.hartid // Pass through the hartid
trace.foreach { _ := core.io.trace }
halt_and_catch_fire.foreach { _ := uncorrectable }
outer.frontend.module.io.cpu <> core.io.imem
outer.frontend.module.io.reset_vector := io.reset_vector
outer.frontend.module.io.hartid := io.hartid
outer.dcache.module.io.hartid := io.hartid
outer.frontend.module.io.reset_vector := constants.reset_vector
outer.frontend.module.io.hartid := constants.hartid
outer.dcache.module.io.hartid := constants.hartid
dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
core.io.ptw <> ptw.io.dpath