riscv/rocket-chip
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tile: BaseTile refactor, pt 2

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* 2 layer cake
* no more bundle traits, only call to IO
This commit is contained in:
Henry Cook
2018-01-02 15:37:31 -08:00
parent 1579ddb97e
commit efe7165b54
12 changed files with 49 additions and 93 deletions
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23
src/main/scala/tile/RocketTile.scala
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@ -56,27 +56,24 @@ class RocketTile(
override lazy val module = new RocketTileModule(this)
}
class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
with CanHaltAndCatchFire {
val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(Bool(OUTPUT))
}
class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
with HasLazyRoCCModule
class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer)
with HasLazyRoCCModule[RocketTile]
with CanHaveScratchpadModule {
val core = Module(p(BuildCore)(outer.p))
val uncorrectable = RegInit(Bool(false))
val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(IO(Bool(OUTPUT)))
outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
outer.busErrorUnit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt }
core.io.hartid := io.hartid // Pass through the hartid
io.trace.foreach { _ := core.io.trace }
io.halt_and_catch_fire.foreach { _ := uncorrectable }
core.io.hartid := constants.hartid // Pass through the hartid
trace.foreach { _ := core.io.trace }
halt_and_catch_fire.foreach { _ := uncorrectable }
outer.frontend.module.io.cpu <> core.io.imem
outer.frontend.module.io.reset_vector := io.reset_vector
outer.frontend.module.io.hartid := io.hartid
outer.dcache.module.io.hartid := io.hartid
outer.frontend.module.io.reset_vector := constants.reset_vector
outer.frontend.module.io.hartid := constants.hartid
outer.dcache.module.io.hartid := constants.hartid
dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
core.io.ptw <> ptw.io.dpath