tile: BaseTile refactor, pt 2

* 2 layer cake
* no more bundle traits, only call to IO

src/main/scala/tile/BaseTile.scala

@@ -121,35 +121,11 @@ trait HasTileParameters {
 
 }
 
-abstract class BareTile(implicit p: Parameters) extends LazyModule
-
-abstract class BareTileBundle[+L <: BareTile](_outer: L) extends GenericParameterizedBundle(_outer) {
-  val outer = _outer
-  implicit val p = outer.p
-}
-
-abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
-  val outer = _outer
-  val io = IO(_io ())
-}
-
-/** Some other standard inputs */
-trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
-  val hartid = UInt(INPUT, hartIdLen)
-  val reset_vector = UInt(INPUT, resetVectorLen)
-}
-
-trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
-  val trace = tileParams.trace.option(Vec(tileParams.core.retireWidth, new TracedInstruction).asOutput)
-}
-
 /** Base class for all Tiles that use TileLink */
-abstract class BaseTile(
-  tileParams: TileParams,
-  val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends BareTile
-    with HasTileParameters
-    with HasCrossing {
-  def module: BaseTileModule[BaseTile, BaseTileBundle[BaseTile]]
+abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCrossing)
+                       (implicit p: Parameters) extends LazyModule with HasTileParameters with HasCrossing
+{
+  def module: BaseTileModule[BaseTile]
   def masterNode: TLOutwardNode
   def slaveNode: TLInwardNode
   def intInwardNode: IntInwardNode
@@ -195,16 +171,22 @@ abstract class BaseTile(
   }
 }
 
-abstract class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
-    with HasExternallyDrivenTileConstants
-    with CanHaveInstructionTracePort
-    with CanHaltAndCatchFire
+class BaseTileModule[+L <: BaseTile](val outer: L) extends LazyModuleImp(outer) with HasTileParameters {
 
-class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
-    with HasTileParameters {
   require(xLen == 32 || xLen == 64)
   require(paddrBits <= maxPAddrBits)
   require(resetVectorLen <= xLen)
   require(resetVectorLen <= vaddrBitsExtended)
   require (log2Up(hartId + 1) <= hartIdLen, s"p(MaxHartIdBits) of $hartIdLen is not enough for hartid $hartId")
+
+  val trace = tileParams.trace.option(IO(Vec(tileParams.core.retireWidth, new TracedInstruction).asOutput))
+  val constants = IO(new TileInputConstants)
 }
+
+/** Some other non-tilelink but still standard inputs */
+trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
+  val hartid = UInt(INPUT, hartIdLen)
+  val reset_vector = UInt(INPUT, resetVectorLen)
+}
+
+class TileInputConstants(implicit val p: Parameters) extends ParameterizedBundle with HasExternallyDrivenTileConstants

src/main/scala/tile/FPU.scala

@@ -875,11 +875,8 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
   }
 }
 
-/** Mix-ins for constructing tiles that may have an FPU external to the core pipeline */
-trait CanHaveSharedFPU extends HasTileParameters
-
-trait CanHaveSharedFPUModule {
-  val outer: CanHaveSharedFPU
+/** Mix-in for constructing tiles that may have an FPU external to the core pipeline */
+trait CanHaveSharedFPUModule[+L <: BaseTile] { this: BaseTileModule[L] =>
   val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
   // TODO fpArb could go here instead of inside LegacyRoccComplex
 }

src/main/scala/tile/LazyRoCC.scala

@@ -77,10 +77,7 @@ class LazyRoCCModule(outer: LazyRoCC) extends LazyModuleImp(outer) {
 
 /** Mixins for including RoCC **/
 
-trait HasLazyRoCC extends CanHaveSharedFPU with CanHavePTW { this: BaseTile =>
-  implicit val p: Parameters
-  val module: HasLazyRoCCModule
-
+trait HasLazyRoCC extends CanHavePTW { this: BaseTile =>
   val roccs = p(BuildRoCC).zipWithIndex.map { case (accelParams, i) =>
     accelParams.generator(p.alterPartial({
       case RoccNPTWPorts => accelParams.nPTWPorts
@@ -93,10 +90,10 @@ trait HasLazyRoCC extends CanHaveSharedFPU with CanHavePTW { this: BaseTile =>
   nDCachePorts += roccs.size
 }
 
-trait HasLazyRoCCModule extends CanHaveSharedFPUModule
-  with CanHavePTWModule
-  with HasCoreParameters {
-  val outer: HasLazyRoCC
+trait HasLazyRoCCModule[+L <: BaseTile with HasLazyRoCC] extends CanHaveSharedFPUModule[L]
+    with CanHavePTWModule
+    with HasCoreParameters { this: BaseTileModule[L] =>
+
   val roccCore = Wire(new RoCCCoreIO()(outer.p))
 
   val buildRocc = outer.p(BuildRoCC)

src/main/scala/tile/RocketTile.scala

@@ -56,27 +56,24 @@ class RocketTile(
   override lazy val module = new RocketTileModule(this)
 }
 
-class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
-    with CanHaltAndCatchFire {
-  val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(Bool(OUTPUT))
-}
-
-class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
-    with HasLazyRoCCModule
+class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer)
+    with HasLazyRoCCModule[RocketTile]
     with CanHaveScratchpadModule {
 
   val core = Module(p(BuildCore)(outer.p))
+
   val uncorrectable = RegInit(Bool(false))
+  val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(IO(Bool(OUTPUT)))
 
   outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
   outer.busErrorUnit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt }
-  core.io.hartid := io.hartid // Pass through the hartid
-  io.trace.foreach { _ := core.io.trace }
-  io.halt_and_catch_fire.foreach { _ := uncorrectable }
+  core.io.hartid := constants.hartid // Pass through the hartid
+  trace.foreach { _ := core.io.trace }
+  halt_and_catch_fire.foreach { _ := uncorrectable }
   outer.frontend.module.io.cpu <> core.io.imem
-  outer.frontend.module.io.reset_vector := io.reset_vector
-  outer.frontend.module.io.hartid := io.hartid
-  outer.dcache.module.io.hartid := io.hartid
+  outer.frontend.module.io.reset_vector := constants.reset_vector
+  outer.frontend.module.io.hartid := constants.hartid
+  outer.dcache.module.io.hartid := constants.hartid
   dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
   fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
   core.io.ptw <> ptw.io.dpath